tDDTTE tDDTEN
參數(shù)資料
型號: ADSP-21065LKSZ-264
廠商: Analog Devices Inc
文件頁數(shù): 27/44頁
文件大小: 0K
描述: IC DSP CONTROLL 544KBIT 208-MQFP
產(chǎn)品培訓(xùn)模塊: SHARC Processor Overview
標(biāo)準(zhǔn)包裝: 1
系列: SHARC®
類型: 浮點
接口: 主機(jī)接口,串行端口
時鐘速率: 60MHz
非易失內(nèi)存: 外部
芯片上RAM: 64kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 3.30V
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 208-BFQFP
供應(yīng)商設(shè)備封裝: 208-MQFP(28x28)
包裝: 托盤
REV. C
ADSP-21065L
–33–
DT
tDDTTE
tDDTEN
tDDTTI
tDDTIN
DRIVE
EDGE
DRIVE
EDGE
DRIVE
EDGE
DRIVE
EDGE
TCLK / RCLK
TCLK (EXT)
TFS ("LATE", EXT.)
tSDRI
RCLK
RFS
DR
DRIVE
EDGE
SAMPLE
EDGE
tHDRI
tSFSI
tHFSI
tDFSE
tHOFSE
tSCLKIW
DATA RECEIVE– INTERNAL CLOCK
tSDRE
DATA RECEIVE– EXTERNAL CLOCK
RCLK
RFS
DR
DRIVE
EDGE
SAMPLE
EDGE
tHDRE
tSFSE
tHFSE
tDFSE
tSCLKW
tHOFSE
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
tDDTI
tHDTI
TCLK
TFS
DT
DRIVE
EDGE
SAMPLE
EDGE
tSFSI
tHFSI
tSCLKIW
tDFSI
tHOFSI
DATA TRANSMIT– INTERNAL CLOCK
tDDTE
tHDTE
TCLK
TFS
DT
DRIVE
EDGE
SAMPLE
EDGE
tSFSE
tHFSE
tDFSE
tSCLKW
tHOFSE
DATA TRANSMIT– EXTERNAL CLOCK
CLKIN
SPORT ENABLE AND
THREE-STATE
LATENCY
IS TWO CYCLES
tDPTR
SPORT DISABLE DELAY
FROM INSTRUCTION
tDCLK
LOW TO HIGH ONLY
TCLK (INT)
RCLK (INT)
TCLK, RCLK
TFS, RFS, DT
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
TCLK (INT)
TFS ("LATE", INT.)
Figure 20. Serial Ports
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