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參數(shù)資料
| 型號： | ADSP-21065LKSZ-264 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP CONTROLL 544KBIT 208-MQFP |
| 產品培訓模塊： | SHARC Processor Overview |
| 標準包裝： | 1 |
| 系列： | SHARC® |
| 類型： | 浮點 |
| 接口： | 主機接口，串行端口 |
| 時鐘速率： | 60MHz |
| 非易失內存： | 外部 |
| 芯片上RAM： | 64kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 3.30V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 208-BFQFP |
| 供應商設備封裝： | 208-MQFP（28x28） |
| 包裝： | 托盤 |
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REV. C
ADSP-21065L
–16–
Memory Read—Bus Master
Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN.
These specifications apply when the ADSP-21065L is the bus master when accessing external memory space. These switching
characteristics also apply for bus master synchronous read/write timing (see Synchronous Read/Write—Bus Master below). If these
timing requirements are met, the synchronous read/write timing can be ignored (and vice versa). An exception to this is the ACK pin
timing requirements as described in the note below.
Parameter
Min
Max
Unit
Timing Requirements:
tDAD
Address, Selects Delay to Data Valid
1, 2
28.0 + 32 DT + W
ns
tDRLD
RD Low to Data Valid1
24.0 + 26 DT + W
ns
tHDA
Data Hold from Address Selects
3
0.0
ns
tHDRH
Data Hold from
RD High3
0.0
ns
tDAAK
ACK Delay from Address, Selects
2, 3
24.0 + 30 DT + W
ns
tDSAK
ACK Delay from
RD Low3
19.5 + 24 DT + W
ns
Switching Characteristics:
tDRHA
Address, Selects Hold After
RD High
–1.0 + H
ns
tDARL
Address, Selects to
RD Low2
3.0 + 6 DT
ns
tRW
RD Pulsewidth
25.0 + 26 DT + W
ns
tRWR
RD High to WR, RD Low
4.5 + 6 DT + HI
ns
tRDGL
RD High to DMAGx Low
11.0 +12 DT + HI
ns
W = (number of wait states specified in WAIT register)
tCK.
HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
H = tCK (if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).
NOTES
1Data Delay/Setup: User must meet t
DAD or to tDRLD or synchronous specification tSSDATI.
2The falling edge of
MSx, SW, BMS, are referenced.
3ACK is not sampled on external memory accesses that use the Internal wait state mode. For the first CLKIN cycle of a new external memory access, ACK must be
valid by tDAAK or tDSAK or synchronous specification tSACKC for wait state modes External, Either, or Both (Both, if the internal wait state is zero). For the second and
subsequent cycles of a wait stated external memory access, synchronous specifications t SACKC and tHACKC must be met for wait state modes External, Either, or Both
(Both, after internal wait states have completed).
WR
ACK
DATA
RD
ADDRESS
MSx , SW
BMS
tDARL
tRW
tDAAK
tRWR
tDRHA
tDSAK
DMAG
tHDRH
tRDGL
tDRLD
tDAD
tHDA
Figure 11. Memory Read—Bus Master
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