參數(shù)資料
型號(hào)： ADSP-21369KSWZ-5A
廠商： Analog Devices Inc
文件頁數(shù)： 13/64頁
文件大?。?/td> 0K
描述： IC DSP 32BIT 366MHZ 208LQFP
標(biāo)準(zhǔn)包裝： 1
系列： SHARC®
類型： 浮點(diǎn)
接口： DAI，DPI
時(shí)鐘速率： 366MHz
非易失內(nèi)存： ROM（768 kB）
芯片上RAM： 256kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.20V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 208-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 208-LQFP-EP（28x28）
包裝： 托盤
Rev. F
|
Page 20 of 64
|
October 2013
Power-Up Sequencing
The timing requirements for processor start-up are given in
Table 12. Note that during power-up, a leakage current of
approximately 200μA may be observed on the RESET pin if it is
driven low before power up is complete. This leakage current
results from the weak internal pull-up resistor on this pin being
enabled during power-up.
Table 12. Power-Up Sequencing Timing Requirements (Processor Start-up)
Parameter
Min
Max
Unit
Timing Requirements
t
RSTVDD
RESET Low Before V
DDINT/VDDEXT On
0
ns
t
IVDDEVDD
V
DDINT On Before VDDEXT
–50
+200
ms
t
CLKVDD
1
CLKIN Valid After V
DDINT/VDDEXT Valid
0
200
ms
t
CLKRST
CLKIN Valid Before RESET Deasserted
10
2
μs
t
PLLRST
PLL Control Setup Before RESET Deasserted
20
μs
Switching Characteristic
t
CORERST
Core Reset Deasserted After RESET Deasserted
4096t
CK + 2 tCCLK
3, 4
1 Valid V
DDINT/VDDEXT assumes that the supplies are fully ramped to their 1.2 V rails and 3.3 V rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds
depending on the design of the power supply subsystem.
2 Assumes a stable CLKIN signal, after meeting worst-case start-up timing of crystal oscillators. Refer to your crystal oscillator manufacturer’s data sheet for start-up time.
Assume a 25 ms maximum oscillator start-up time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
3 Applies after the power-up sequence is complete. Subsequent resets require RESET to be held low a minimum of four CLKIN cycles in order to properly initialize and propagate
default states at all I/O pins.
4 The 4096 cycle count depends on tsrst specification in Table 14. If setup time is not met, 1 additional CLKIN cycle may be added to the core reset time, resulting in 4097 cycles
maximum.
Figure 6. Power-Up Sequencing
tRSTVDD
tCLKVDD
tCLKRST
tCORERST
tPLLRST
VDDEXT
VDDINT
CLKIN
CLK_CFG1–0
RESET
RESETOUT
tIVDDEVDD
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