參數(shù)資料
型號: ADSP-21369KSWZ-5A
廠商: Analog Devices Inc
文件頁數(shù): 9/64頁
文件大?。?/td> 0K
描述: IC DSP 32BIT 366MHZ 208LQFP
標準包裝: 1
系列: SHARC®
類型: 浮點
接口: DAI,DPI
時鐘速率: 366MHz
非易失內(nèi)存: ROM(768 kB)
芯片上RAM: 256kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.20V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 208-LQFP 裸露焊盤
供應商設備封裝: 208-LQFP-EP(28x28)
包裝: 托盤
Rev. F
|
Page 17 of 64
|
October 2013
ELECTRICAL CHARACTERISTICS
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
V
OH
1
High Level Output Voltage
@ V
DDEXT = Min, IOH = –1.0 mA
2
2.4
V
OL
Low Level Output Voltage
@ V
DDEXT = Min, IOL = 1.0 mA
0.4
V
I
IH
3, 4
High Level Input Current
@ V
DDEXT = Max, VIN = VDDEXT Max
10
μA
I
IL
3, 5, 6
Low Level Input Current
@ V
DDEXT = Max, VIN = 0 V
10
μA
I
IHPD
High Level Input Current Pull-Down
@ V
DDEXT = Max, VIN = 0 V
250
μA
I
ILPU
Low Level Input Current Pull-Up
@ V
DDEXT = Max, VIN = 0 V
200
μA
I
OZH
7, 8
Three-State Leakage Current
@ V
DDEXT = Max, VIN = VDDEXT Max
10
μA
I
OZL
Three-State Leakage Current
@ V
DDEXT = Max, VIN = 0 V
10
μA
I
OZLPU
Three-State Leakage Current Pull-Up
@ V
DDEXT = Max, VIN = 0 V
200
μA
I
DD
-INTYP
10
Supply Current (Internal)
t
CCLK = 3.75 ns, VDDINT = 1.2 V, 25°C
t
CCLK = 3.00 ns, VDDINT = 1.2 V, 25°C
t
CCLK = 2.85 ns, VDDINT = 1.3 V, 25°C
t
CCLK = 2.73 ns, VDDINT = 1.3 V, 25°C
t
CCLK = 2.50 ns, VDDINT = 1.3 V, 25°C
700
900
1050
1080
1100
mA
AI
DD
11
Supply Current (Analog)
A
VDD = Max
11
mA
C
IN
12, 13
Input Capacitance
f
IN = 1 MHz, TCASE = 25°C, VIN = 1.3 V
4.7
pF
1 Applies to output and bidirectional pins: ADDRx, DATAx, RD, WR, MSx, BRx, FLAGx, DAI_Px, DPI_Px, SDRAS, SDCAS, SDWE, SDCKE, SDA10, SDCLKx, EMU, TDO.
2 See Output Drive Currents on Page 51 for typical drive current capabilities.
3 Applies to input pins without internal pull-ups: BOOT_CFGx, CLK_CFGx, CLKIN, RESET, TCK.
4 Applies to input pins with internal pull-ups: ACK, RPBA, TMS, TDI, TRST.
5 Applies to input pins with internal pull-downs: IDx.
6 Applies to input pins with internal pull-ups disabled: ACK, RPBA.
7 Applies to three-statable pins without internal pull-ups: FLAGx, SDCLKx, TDO.
8 Applies to three-statable pins with internal pull-ups: ADDRx, DATAx, RD, WR, MSx, BRx, DAI_Px, DPI_Px, SDRAS, SDCAS, SDWE, SDCKE, SDA10, EMU.
9 Applies to three-statable pins with internal pull-ups disabled: ADDRx, DATAx, RD, WR, MSx, BRx, DAI_Px, DPI_Px, SDRAS, SDCAS, SDWE, SDCKE, SDA10
10See the Engineer-to-Engineer Note “Estimating Power Dissipation for ADSP-21368 SHARC Processors” (EE-299) for further information.
11Characterized, but not tested.
12Applies to all signal pins.
13Guaranteed, but not tested.
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