1
參數(shù)資料
型號: ADSP-21369KSWZ-5A
廠商: Analog Devices Inc
文件頁數(shù): 14/64頁
文件大小: 0K
描述: IC DSP 32BIT 366MHZ 208LQFP
標準包裝: 1
系列: SHARC®
類型: 浮點
接口: DAI,DPI
時鐘速率: 366MHz
非易失內(nèi)存: ROM(768 kB)
芯片上RAM: 256kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.20V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 208-LQFP 裸露焊盤
供應商設備封裝: 208-LQFP-EP(28x28)
包裝: 托盤
Rev. F
|
Page 21 of 64
|
October 2013
Clock Input
Table 13. Clock Input
Parameter
400 MHz
1
1 Applies to all 400 MHz models. See Ordering Guide on Page 61.
366 MHz
2
2 Applies to all 366 MHz models. See Ordering Guide on Page 61.
350 MHz
3
3 Applies to all 350 MHz models. See Ordering Guide on Page 61.
333 MHz
4
4 Applies to all 333 MHz models. See Ordering Guide on Page 61.
266 MHz
5
5 Applies to all 266 MHz models. See Ordering Guide on Page 61.
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Timing Requirements
t
CK
CLKIN Period
156
6 Applies only for CLK_CFG1–0 = 00 and default values for PLL control bits in PMCTL.
100
16.396
100
17.146
100
186
100
22.56
100
ns
t
CKL
CLKIN Width Low
7.51
45
8.11
45
8.51
45
91
45
11.251
45
ns
t
CKH
CLKIN Width High
7.5
1
45
8.1
1
45
8.5
1
45
9
1
45
11.25
1
45
ns
t
CKRF
CLKIN Rise/Fall (0.4 V to 2.0 V)
3
ns
t
CCLK
7
7 Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t
CCLK.
CCLK Period
2.5
10
2.73
10
2.85
10
3.0
10
3.75
10
ns
f
VCO
8
8 See Figure 5 on Page 19 for VCO diagram.
VCO Frequency
100
800
100
800
100
800
100
800
100
600
MHz
t
CKJ
9, 10
9 Actual input jitter should be combined with ac specifications for accurate timing analysis.
10Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.
CLKIN Jitter Tolerance
–250
+250
–250
+250
–250
+250
–250
+250
–250
+250
ps
Figure 7. Clock Input
CLKIN
tCK
tCKL
tCKH
tCKJ
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