參數(shù)資料
型號: ADSP-21369KSWZ-5A
廠商: Analog Devices Inc
文件頁數(shù): 24/64頁
文件大?。?/td> 0K
描述: IC DSP 32BIT 366MHZ 208LQFP
標準包裝: 1
系列: SHARC®
類型: 浮點
接口: DAI,DPI
時鐘速率: 366MHz
非易失內(nèi)存: ROM(768 kB)
芯片上RAM: 256kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.20V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 208-LQFP 裸露焊盤
供應商設(shè)備封裝: 208-LQFP-EP(28x28)
包裝: 托盤
Rev. F
|
Page 30 of 64
|
October 2013
Memory Read
Use these specifications for asynchronous interfacing to memo-
ries. These specifications apply when the processors are the bus
master accessing external memory space in asynchronous access
mode. Note that timing for ACK, DATA, RD, WR, and strobe
timing parameters only apply to asynchronous access mode.
Table 24. Memory Read
Parameter
Min
Max
Unit
Timing Requirements
t
DAD
Address, Selects Delay to Data Valid
1, 2
W + t
SDCLK –5.12
ns
t
DRLD
RD Low to Data Valid
W – 3.2
ns
t
SDS
Data Setup to RD High
2.5
ns
t
HDRH
Data Hold from RD High
3, 4
0ns
t
DAAK
ACK Delay from Address, Selects
t
SDCLK – 9.5 + W
ns
t
DSAK
ACK Delay from RD Low
W – 7.0
ns
Switching Characteristics
t
DRHA
Address Selects Hold After RD High
RH + 0.20
ns
t
DARL
Address Selects to RD Low
t
SDCLK – 3.3
ns
t
RW
RD Pulse Width
W – 1.4
ns
t
RWR
RD High to WR, RD Low
HI + t
SDCLK – 0.8
ns
W = (number of wait states specified in AMICTLx register) × tSDCLK.
HI =RHC + IC (RHC = number of read hold cycles specified in AMICTLx register) × tSDCLK.
IC = (number of idle cycles specified in AMICTLx register) × tSDCLK.
H = (number of hold cycles specified in AMICTLx register) × tSDCLK.
1 The falling edge of MSx is referenced.
2 The maximum limit of timing requirement values for tDAD and tDRLD parameters are applicable for the case where AMI_ACK is always high and when the ACK feature is not used.
3 Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only apply to asynchronous access mode.
4 Data hold: User must meet t
HDA or tHDRH in asynchronous access mode. See Test Conditions on Page 51 for the calculation of hold times given capacitive and dc loads.
5 ACK delay/setup: User must meet tDAAK, or tDSAK, for deassertion of ACK (low). For asynchronous assertion of ACK (high), user must meet tDAAK or tDSAK.
相關(guān)PDF資料
PDF描述
TAP106M035BRW CAP TANT 10UF 35V 20% RADIAL
XC2C384-10FGG324C IC CR-II CPLD 384MCELL 324-FBGA
HMM28DSAI CONN EDGECARD 56POS R/A .156 SLD
ADSP-21369KBPZ-2A IC DSP 32BIT 333MHZ 256-BGA
VE-21M-CY-F1 CONVERTER MOD DC/DC 10V 50W
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADSP-21369KSWZ-6A 功能描述:IC DSP 32BIT 400MHZ 208-LQFP 制造商:analog devices inc. 系列:SHARC? 包裝:托盤 零件狀態(tài):有效 類型:浮點 接口:DAI,DPI 時鐘速率:400MHz 非易失性存儲器:ROM(768 kB) 片載 RAM:256KB 電壓 - I/O:3.30V 電壓 - 內(nèi)核:1.20V 工作溫度:0°C ~ 70°C(TA) 安裝類型:表面貼裝 封裝/外殼:208-LQFP 裸露焊盤 供應商器件封裝:208-LQFP-EP(28x28) 標準包裝:1
ADSP-21369KSZ-1A 制造商:Analog Devices 功能描述:DSP Floating-Point 32-Bit/40-Bit 266MHz 266MIPS 208-Pin MQFP 制造商:Analog Devices 功能描述:PROCESSOR ((NS))
ADSP-21369KSZ-1A 制造商:Analog Devices 功能描述:DSP PROCESSOR ((NS))
ADSP-21371 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor optimized for high performance audio processing
ADSP-21371_07 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC㈢ Processor