參數(shù)資料
型號: ADV7393-DBRDZ
廠商: Analog Devices Inc
文件頁數(shù): 15/108頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR ADV7393
產(chǎn)品變化通告: ADV734x, ADV739x Feature Improvement
設(shè)計資源: Reconstruction Video Filter Using ADA4430-1 Amplifier After ADV7393 Video Encoder (CN0101)
標準包裝: 1
系列: Advantiv®
主要目的: 視頻,視頻編碼器
已用 IC / 零件: ADV7393
已供物品:
相關(guān)產(chǎn)品: ADV7393BCPZ-ND - IC DAC VIDEO HDTV 10BIT 40LFCSP
ADV7393BCPZ-REEL-ND - IC DAC ENCODER VID HDTV 40-LFCSP
ADV7390/ADV7391/ADV7392/ADV7393
Data Sheet
Rev. G | Page 14 of 108
Figure 9. ED/HD-DDR Input, 8-/10-Bit 4:2:2 YCrCb (EAV/SAV), Input Mode 010
Figure 10. ED (at 54 MHz) Input, 8-/10-Bit 4:2:2 YCrCb (HSYNC/VSYNC), Input Mode 111
Figure 11. ED (at 54 MHz) Input, 8-/10-Bit 4:2:2 YCrCb (EAV/SAV), Input Mode 111
CONTROL
OUTPUTS
PIXEL PORT
*LUMA/CHROMA CLOCK RELATIONSHIP CAN BE INVERTED USING SUBADDRESS 0x01, BITS 1 AND 2.
Y1
Cr0
Y0
Cb0
XY
00
3FF
CLKIN*
t9
t10
t12
t11
t12
t11
t14
t13
06234-
007
CLKIN
CONTROL
OUTPUTS
Y1
Cr0
Y0
Cb0
Cr2
Y2
Cb2
t9
t10
t12
t11
t13
t14
PIXEL PORT
HSYNC
VSYNC
CONTROL
INPUTS
06234-
008
CLKIN
CONTROL
OUTPUTS
3FF
00
XY
Cb0
Y0
Cr0
Y1
PIXEL PORT
t11
t12
t10
t9
t14
t13
06234-
009
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