VDD
參數(shù)資料
型號(hào)： ADV7393-DBRDZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 2/108頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADV7393
產(chǎn)品變化通告： ADV734x, ADV739x Feature Improvement
設(shè)計(jì)資源： Reconstruction Video Filter Using ADA4430-1 Amplifier After ADV7393 Video Encoder (CN0101)
標(biāo)準(zhǔn)包裝： 1
系列： Advantiv®
主要目的： 視頻，視頻編碼器
已用 IC / 零件： ADV7393
已供物品： 板
相關(guān)產(chǎn)品： ADV7393BCPZ-ND - IC DAC VIDEO HDTV 10BIT 40LFCSP
ADV7393BCPZ-REEL-ND - IC DAC ENCODER VID HDTV 40-LFCSP
ADV7390/ADV7391/ADV7392/ADV7393
Data Sheet
Rev. G | Page 10 of 108
DIGITAL TIMING SPECIFICATIONS—1.8 V
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 1.71 V to 1.89 V.
All specifications TMIN to TMAX (40°C to +85°C), unless otherwise noted.
Table 10.
Parameter
Conditions1
Min
Typ
Max
Unit
VIDEO DATA AND VIDEO CONTROL PORT2, 3
Data Input Setup Time, t114
SD
1.4
ns
ED/HD-SDR
1.9
ns
ED/HD-DDR
1.9
ns
ED (at 54 MHz)
1.6
ns
Data Input Hold Time, t124
SD
1.4
ns
ED/HD-SDR
1.5
ns
ED/HD-DDR
1.5
ns
ED (at 54 MHz)
1.3
ns
Control Input Setup Time, t114
SD
1.4
ns
ED/HD-SDR or ED/HD-DDR
1.2
ns
ED (at 54 MHz)
1.0
ns
Control Input Hold Time, t124
SD
1.4
ns
ED/HD-SDR or ED/HD-DDR
1.0
ns
ED (at 54 MHz)
1.0
ns
Control Output Access Time, t134
SD
13
ns
ED/HD-SDR, ED/HD-DDR, or ED (at 54 MHz)
12
ns
Control Output Hold Time, t144
SD
4.0
ns
ED/HD-SDR, ED/HD-DDR, or ED (at 54 MHz)
5.0
ns
PIPELINE DELAY5
CVBS/Y-C Outputs (2×)
SD oversampling disabled
68
Clock cycles
CVBS/Y-C Outputs (8×)
SD oversampling enabled
79
Clock cycles
CVBS/Y-C Outputs (16×)
SD oversampling enabled
67
Clock cycles
Component Outputs (2×)
SD oversampling disabled
78
Clock cycles
Component Outputs (8×)
SD oversampling enabled
69
Clock cycles
Component Outputs (16×)
SD oversampling enabled
84
Clock cycles
Component Outputs (1×)
ED oversampling disabled
41
Clock cycles
Component Outputs (4×)
ED oversampling enabled
49
Clock cycles
Component Outputs (8×)
ED oversampling enabled
46
Clock cycles
Component Outputs (1×)
HD oversampling disabled
40
Clock cycles
Component Outputs (2×)
HD oversampling enabled
42
Clock cycles
Component Outputs (4×)
HD oversampling enabled
44
Clock cycles
RESET CONTROL
RESET Low Time
100
ns
1
SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition, SDR = single data rate, DDR = dual data rate.
2
Video data: P[15:0] for ADV7392/ADV7393 or P[7:0] for ADV7390/ADV7391.
3
Video control: HSYNC and VSYNC.
4
Guaranteed by characterization.
5
Guaranteed by design.
相關(guān)PDF資料
PDF描述
REC5-053.3DRW/H6/C CONV DC/DC 5W 4.5-9VIN +/-3.3V
GBM30DRMI-S288 CONN EDGECARD 60POS .156 EXTEND
RMM08DTKI-S288 CONN EDGECARD 16POS .156 EXTEND
HCC05DREF-S13 CONN EDGECARD 10POS .100 EXTEND
EEC17DREN-S734 CONN EDGECARD 34POS .100 EYELET
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADV7393EBZ 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Power, Chip Scale 10-Bit SD/HD Video Encoder
ADV7393WBCPZ 制造商:Analog Devices 功能描述:LOW POWER, CHIP SCALE 10-BIT SD/HD VIDEO ENCODER - Trays
ADV7393WBCPZ-REEL 制造商:Analog Devices 功能描述:LOW POWER, CHIP SCALE 10-BIT SD/HD VIDEO ENCODER - Tape and Reel
ADV73946603 制造商:LG Corporation 功能描述:Frame Assembly
ADV73946604 制造商:LG Corporation 功能描述:Frame Assembly
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*