參數(shù)資料
型號(hào)： ADV7393-DBRDZ
廠商： Analog Devices Inc
文件頁數(shù)： 43/108頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADV7393
產(chǎn)品變化通告： ADV734x, ADV739x Feature Improvement
設(shè)計(jì)資源： Reconstruction Video Filter Using ADA4430-1 Amplifier After ADV7393 Video Encoder (CN0101)
標(biāo)準(zhǔn)包裝： 1
系列： Advantiv®
主要目的： 視頻，視頻編碼器
已用 IC / 零件： ADV7393
已供物品： 板
相關(guān)產(chǎn)品： ADV7393BCPZ-ND - IC DAC VIDEO HDTV 10BIT 40LFCSP
ADV7393BCPZ-REEL-ND - IC DAC ENCODER VID HDTV 40-LFCSP
ADV7390/ADV7391/ADV7392/ADV7393
Data Sheet
Rev. G | Page 4 of 108
Added Digital Input/Output Specifications—1.8 V Section and
Table 6 ................................................................................................ 7
Changes to MPU Port Timing Specifications Section,
Default Conditions ........................................................................... 7
Changes to Digital Timing Specifications—3.3 V Section and
Table 8 ................................................................................................ 8
Added Digital Timing Specifications—1.8 V Section and
Table 9 ................................................................................................ 9
Added Video Performance Specifications Section, Default
Conditions ....................................................................................... 10
Added Power Specifications Section, Default Conditions........ 10
Changes to Table 11........................................................................ 10
Changes to Figure 16...................................................................... 16
Changes to Table 12........................................................................ 17
Changes to Table 14, Pin 19 and Pin 1 Descriptions ................. 18
Changes to MPU Port Description Section ................................ 25
Changes to I2C Operation Section ............................................... 25
Added Table 15 ............................................................................... 25
Changes to Table 17........................................................................ 28
Changes to Table 19, 0x30 Bit Description ................................. 30
Changes to Table 27........................................................................ 37
Changes to Table 29, 0x8B Bit Description................................. 39
Changes to Table 30........................................................................ 40
Changes to Table 31........................................................................ 41
Added Table 32 ............................................................................... 42
Renamed Features Section to Design Features Section............. 48
Changes to ED/HD Nonstandard Timing Mode Section......... 48
Added the HD Interlace External HSYNC and VSYNC
Considerations Section.................................................................. 49
Changes to SD Subcarrier Frequency Lock, Subcarrier Reset,
and Timing Reset Section.............................................................. 49
Changes to Subaddress 0x8C to Subaddress 0x8F Section....... 51
Changes to Programming the FSC Section................................... 51
Changes to Subaddress 0x82, Bit 4 Section................................. 51
Added SD Manual CSC Matrix Adjust Feature Section............ 54
Added Table 47 ............................................................................... 55
Changes to Subaddress 0x9C to Subaddress 0x9F Section....... 56
Changes to Subaddress 0xBA Section.......................................... 56
Added Sleep Mode Section ........................................................... 65
Changes to Pixel and Control Port Readback Section .............. 66
Changes to Reset Mechanisms Section ....................................... 66
Added SD Teletext Insertion Section........................................... 66
Added Figure 87 ............................................................................. 67
Added Figure 88 ............................................................................. 68
Changes to DAC Configuration Section..................................... 68
Added Unused Pins Section.......................................................... 68
Changes to Power Supply Sequencing Section........................... 70
Changes to Internal Test Pattern Generation Section ............... 77
Changes to SD Timing, Mode 0 (CCIR-656)—Slave Option
(Subaddress 0x8A = XXXXX000) Section.................................. 78
10/06—Revision 0: Initial Version
相關(guān)PDF資料
PDF描述
REC5-053.3DRW/H6/C CONV DC/DC 5W 4.5-9VIN +/-3.3V
GBM30DRMI-S288 CONN EDGECARD 60POS .156 EXTEND
RMM08DTKI-S288 CONN EDGECARD 16POS .156 EXTEND
HCC05DREF-S13 CONN EDGECARD 10POS .100 EXTEND
EEC17DREN-S734 CONN EDGECARD 34POS .100 EYELET
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADV7393EBZ 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Power, Chip Scale 10-Bit SD/HD Video Encoder
ADV7393WBCPZ 制造商:Analog Devices 功能描述:LOW POWER, CHIP SCALE 10-BIT SD/HD VIDEO ENCODER - Trays
ADV7393WBCPZ-REEL 制造商:Analog Devices 功能描述:LOW POWER, CHIP SCALE 10-BIT SD/HD VIDEO ENCODER - Tape and Reel
ADV73946603 制造商:LG Corporation 功能描述:Frame Assembly
ADV73946604 制造商:LG Corporation 功能描述:Frame Assembly
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*