參數(shù)資料
型號： ADV7393-DBRDZ
廠商： Analog Devices Inc
文件頁數(shù)： 3/108頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADV7393
產(chǎn)品變化通告： ADV734x, ADV739x Feature Improvement
設(shè)計資源： Reconstruction Video Filter Using ADA4430-1 Amplifier After ADV7393 Video Encoder (CN0101)
標(biāo)準(zhǔn)包裝： 1
系列： Advantiv®
主要目的： 視頻，視頻編碼器
已用 IC / 零件： ADV7393
已供物品： 板
相關(guān)產(chǎn)品： ADV7393BCPZ-ND - IC DAC VIDEO HDTV 10BIT 40LFCSP
ADV7393BCPZ-REEL-ND - IC DAC ENCODER VID HDTV 40-LFCSP
ADV7390/ADV7391/ADV7392/ADV7393
Data Sheet
Rev. G | Page 100 of 108
Table 105. 16-Bit 625p YCrCb In (EAV/SAV), RGB Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (8×).
0x01
0x10
ED-SDR input mode.
0x02
0x10
RGB output enabled. RGB output sync
enabled.
0x30
0x1C
625p at 50 Hz. EAV/SAV synchroniza-
tion. EIA-770.2 output levels.
0x31
0x01
Pixel data valid.
Table 106. 16-Bit 625p YCrCb In, RGB Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (8×).
0x01
0x10
ED-SDR input mode.
0x02
0x10
RGB output enabled. RGB output sync
enabled.
0x30
0x18
625p at 50 Hz. HSYNC/VSYNC synch-
ronization. EIA-770.2 output levels.
0x31
0x01
Pixel data valid.
Table 107. 8-Bit 525p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (8×).
0x01
0x20
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x30
0x04
525p at 59.94 Hz. EAV/SAV synchro-
nization. EIA-770.2 output levels.
0x31
0x01
Pixel data valid.
Table 108. 10-Bit 525p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (8×).
0x01
0x20
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x30
0x04
525p at 59.94 Hz. EAV/SAV synchro-
nization. EIA-770.2 output levels.
0x31
0x01
Pixel data valid.
0x33
0x6C
10-bit input enabled.
Table 109. 8-Bit 525p YCrCb In (EAV/SAV), RGB Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (8×).
0x01
0x20
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x02
0x10
RGB output enabled. RGB output sync
enabled.
0x30
0x04
525p at 59.94 Hz. EAV/SAV synchro-
nization. EIA-770.2 output levels.
0x31
0x01
Pixel data valid.
Table 110. 10-Bit 525p YCrCb In (EAV/SAV), RGB Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (8×).
0x01
0x20
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x02
0x10
RGB output enabled. RGB output sync
enabled.
0x30
0x04
525p at 59.94 Hz. EAV/SAV synchro-
nization. EIA-770.2 output levels.
0x31
0x01
Pixel data valid.
0x33
0x6C
10-bit input enabled.
Table 111. 8-Bit 625p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (8×).
0x01
0x20
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x30
0x1C
625p at 50 Hz. EAV/SAV synchroniza-
tion. EIA-770.2 output levels.
0x31
0x01
Pixel data valid.
Table 112. 10-Bit 625p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (8×).
0x01
0x20
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x30
0x1C
625p at 50 Hz. EAV/SAV synchroniza-
tion. EIA-770.2 output levels.
0x31
0x01
Pixel data valid.
0x33
0x6C
10-bit input enabled.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADV7393EBZ 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Power, Chip Scale 10-Bit SD/HD Video Encoder
ADV7393WBCPZ 制造商:Analog Devices 功能描述:LOW POWER, CHIP SCALE 10-BIT SD/HD VIDEO ENCODER - Trays
ADV7393WBCPZ-REEL 制造商:Analog Devices 功能描述:LOW POWER, CHIP SCALE 10-BIT SD/HD VIDEO ENCODER - Tape and Reel
ADV73946603 制造商:LG Corporation 功能描述:Frame Assembly
ADV73946604 制造商:LG Corporation 功能描述:Frame Assembly
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