參數(shù)資料
型號(hào)： ADV7393-DBRDZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 51/108頁(yè)
文件大小： 0K
描述： BOARD EVAL FOR ADV7393
產(chǎn)品變化通告： ADV734x, ADV739x Feature Improvement
設(shè)計(jì)資源： Reconstruction Video Filter Using ADA4430-1 Amplifier After ADV7393 Video Encoder (CN0101)
標(biāo)準(zhǔn)包裝： 1
系列： Advantiv®
主要目的： 視頻，視頻編碼器
已用 IC / 零件： ADV7393
已供物品： 板
相關(guān)產(chǎn)品： ADV7393BCPZ-ND - IC DAC VIDEO HDTV 10BIT 40LFCSP
ADV7393BCPZ-REEL-ND - IC DAC ENCODER VID HDTV 40-LFCSP
Data Sheet
ADV7390/ADV7391/ADV7392/ADV7393
Rev. G | Page 47 of 108
ADV7392/ADV7393 INPUT CONFIGURATION
The ADV7392/ADV7393 support a number of different input
modes. The desired input mode is selected using Subaddress 0x01,
Bits[6:4]. The ADV7392/ADV7393 default to standard definition
(SD) mode on power-up. Table 36 provides an overview of all
possible input configurations. Each input mode is described in
detail in this section.
STANDARD DEFINITION
Subaddress 0x01, Bits[6:4] = 000
Standard definition YCrCb data can be input in 4:2:2 format over
an 8-, 10-, or 16-bit bus. SD RGB data can be input in 4:4:4 format
over a 16-bit bus.
A 27 MHz clock signal must be provided on the CLKIN pin. If
required, external synchronization signals can be provided on
the HSYNC and VSYNC pins. Embedded EAV/SAV timing
codes are also supported in 8-bit and 10-bit modes.
8-Bit 4:2:2 YCrCb Mode
Subaddress 0x87, Bit 7 = 0;
Subaddress 0x88, Bits[4:3] = 00
In 8-bit 4:2:2 YCrCb input mode, the interleaved pixel data is
input on Pin P15 to Pin P8, with Pin P8 being the LSB. The
ITU-R BT.601/656 input standard is supported.
10-Bit 4:2:2 YCrCb Mode
Subaddress 0x87, Bit 7 = 0;
Subaddress 0x88, Bits[4:3] = 10
In 10-bit 4:2:2 YCrCb input mode, the interleaved pixel data is
input on Pin P15 to Pin P6, with Pin P6 being the LSB. The ITU-
R BT.601/656 input standard is supported.
16-Bit 4:2:2 YCrCb Mode
Subaddress 0x87, Bit 7 = 0;
Subaddress 0x88, Bits[4:3] = 01
In 16-bit 4:2:2 YCrCb input mode, the Y pixel data is input on
Pin P15 to Pin P8, with Pin P8 being the LSB.
The CrCb pixel data is input on Pin P7 to Pin P0, with Pin P0
being the LSB.
The pixel data is updated at half the rate of the clock, that is, at a
rate of 13.5 MHz (see Figure 5).
16-Bit 4:4:4 RGB Mode
Embedded EAV/SAV timing codes are not supported with SD RGB
mode. Also, master timing mode is not supported for SD RGB
input mode, therefore, external synchronization must be used.
Subaddress 0x87, Bit 7 = 1
In 16-bit 4:4:4 RGB input mode, the red pixel data is input on
Pin P4 to Pin P0, the green pixel data is input on Pin P10 to
Pin P5, and the blue pixel data is input on Pin P15 to Pin P11.
The P0, P5, and P11 pins are the respective bus LSBs.
The pixel data is updated at half the rate of the clock, that is, at a
rate of 13.5 MHz (see Figure 6).
Figure 56. SD Example Application
Table 36. ADV7392/ADV7393 Input Configuration
Input Mode1
P15
P14
P13
P12
P11
P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
P0
000
SD RGB input enable (0x87[7]) = 0
8-bit
YCrCb
10-bit
YCrCb
16-bit3
Y
CrCb
SD RGB input enable (0x87[7]) = 1
16-bit3
B
G
R
001
ED/HD-SDR (16-bit)
Y
CrCb
010
ED/HD-DDR4
ED/HD input format (0x33[2]) = 0
8-bit
YCrCb
ED/HD input format (0x33[2]) = 1
10-bit
YCrCb
111
ED (at 54 MHz)
ED/HD input format (0x33[2]) = 0
8-bit
YCrCb
ED/HD input format (0x33[2]) = 1
10-bit
YCrCb
1
The input mode is determined by Subaddress 0x01, Bits[6:4].
2
In SD mode, the width of the input data is determined by Subaddress 0x88, Bits[4:3].
3
External synchronization signals must be used in this input mode. Embedded EAV/SAV timing codes are not supported.
4
ED = enhanced definition = 525p and 625p.
MPEG2
DECODER
CLKIN
P[15:8]/P[15:6]
27MHz
YCrCb
ADV7392/
ADV7393
VSYNC,
HSYNC
2
8/10
06234-
054
相關(guān)PDF資料
PDF描述
REC5-053.3DRW/H6/C CONV DC/DC 5W 4.5-9VIN +/-3.3V
GBM30DRMI-S288 CONN EDGECARD 60POS .156 EXTEND
RMM08DTKI-S288 CONN EDGECARD 16POS .156 EXTEND
HCC05DREF-S13 CONN EDGECARD 10POS .100 EXTEND
EEC17DREN-S734 CONN EDGECARD 34POS .100 EYELET
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADV7393EBZ 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Power, Chip Scale 10-Bit SD/HD Video Encoder
ADV7393WBCPZ 制造商:Analog Devices 功能描述:LOW POWER, CHIP SCALE 10-BIT SD/HD VIDEO ENCODER - Trays
ADV7393WBCPZ-REEL 制造商:Analog Devices 功能描述:LOW POWER, CHIP SCALE 10-BIT SD/HD VIDEO ENCODER - Tape and Reel
ADV73946603 制造商:LG Corporation 功能描述:Frame Assembly
ADV73946604 制造商:LG Corporation 功能描述:Frame Assembly
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*