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參數(shù)資料
| 型號(hào)： | ADV7393-DBRDZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 55/108頁(yè) |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADV7393 |
| 產(chǎn)品變化通告： | ADV734x, ADV739x Feature Improvement |
| 設(shè)計(jì)資源： | Reconstruction Video Filter Using ADA4430-1 Amplifier After ADV7393 Video Encoder (CN0101) |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Advantiv® |
| 主要目的： | 視頻，視頻編碼器 |
| 已用 IC / 零件： | ADV7393 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | ADV7393BCPZ-ND - IC DAC VIDEO HDTV 10BIT 40LFCSP ADV7393BCPZ-REEL-ND - IC DAC ENCODER VID HDTV 40-LFCSP |
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ADV7390/ADV7391/ADV7392/ADV7393
Data Sheet
Rev. G | Page 50 of 108
DESIGN FEATURES
OUTPUT OVERSAMPLING
The ADV739x includes an on-chip phase-locked loop (PLL)
that allows for oversampling of SD, ED, and HD video data. By
default, the PLL is disabled. The PLL can be enabled using
Subaddress 0x00, Bit 1 = 0.
Table 40 shows the various oversampling rates supported in the
ADV739x.
External Sync Polarity
For SD and ED/HD modes, the ADV739x parts typically expect
HS and VS to be low during their respective blanking periods.
However, when the CEA861 compliance bit is enabled (0x39,
Bit 5 for ED/HD modes and 0x86, Bit 3 for SD modes), the part
expects the HS or VS to be active low or high depending on the
input format selected (0x30, Bits[7:3]).
If a different polarity other than the default is required for
ED/HD modes, 0x3A, Bits[2:0] can be used to invert PHSYNCB,
PVSYNCB or PBLANKB individually regardless of whether
CEA-861-B mode is enabled. It is not possible to invert
S_HSYNC or S_VSYNC.
Table 40. Output Oversampling Modes and Rates
Input Mode
(0x01, Bits[6:4])
PLL and Oversampling
Control (0x00, Bit 1)
SD/ED Oversample Rate
Select (0x0D, Bit 3)1
HD Oversample Rate
Select (0x31, Bit 1)1
Oversampling Mode
and Rate
000
SD
1
X
SD (2×)
000
SD
0
1
X
SD (8×)
000
SD
0
X
SD (16×)
001/010
ED
1
X
ED (1×)
001/010
ED
0
1
X
ED (4×)
001/010
ED
0
X
ED (8×)
001/010
HD
1
X
HD (1×)
001/010
HD
0
X
1
HD (2×)
001/010
HD
0
X
0
HD (4×)
111
ED (at 54 MHz)
1
X
ED (at 54 MHz) (1×)
111
ED (at 54 MHz)
0
1
X
ED (at 54 MHz) (4×)
111
ED (at 54 MHz)
0
X
ED (at 54 MHz) (8×)
1
X = don’t care
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| ADV7393EBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| ADV7393WBCPZ | 制造商:Analog Devices 功能描述:LOW POWER, CHIP SCALE 10-BIT SD/HD VIDEO ENCODER - Trays |
| ADV7393WBCPZ-REEL | 制造商:Analog Devices 功能描述:LOW POWER, CHIP SCALE 10-BIT SD/HD VIDEO ENCODER - Tape and Reel |
| ADV73946603 | 制造商:LG Corporation 功能描述:Frame Assembly |
| ADV73946604 | 制造商:LG Corporation 功能描述:Frame Assembly |
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