參數(shù)資料
型號(hào): AM79C960
廠商: Advanced Micro Devices, Inc.
英文描述: PCnetTM-ISA Single-Chip Ethernet Controller
中文描述: PCnetTM -的ISA單芯片以太網(wǎng)控制器
文件頁(yè)數(shù): 125/127頁(yè)
文件大小: 814K
代理商: AM79C960
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)當(dāng)前第125頁(yè)第126頁(yè)第127頁(yè)
B-1
Am79C960
Recommendation for Reducing
Noise Injection
APPENDIX B
DECOUPLING LOW-PASS R/C
FILTER DESIGN
The PCnet-ISA controller is an integrated, single-chip
Ethernet controller, which contains both digital and ana-
log circuitry. The analog circuitry contains a high speed
Phase-Locked Loop (PLL) and Voltage Controlled
Oscillator (VCO). Because of the mixed signal charac-
teristics of this chip, some extra precautions must be
taken into account when designing with this device.
Described in this section is a simple decoupling low-
pass R/C filter that can significantly increase noise im-
munity of the PLL circuit, thus, prevent noise from
disrupting the VCO. Bit error rate, a common measure-
ment of network performance, as a result can be
drastically reduced. In certain cases the bit error rate
can be reduced by orders of magnitude.
Implementation of this filter is not necessary to achieve
a functional product that meets the IEEE 802.3 specifi-
cation and provides adequate performance. However,
this filter will help designers meet those specifications
with more margin.
Digital Decoupling
The DVSS pins that are sinking the most current are
those that provide the ground for the ISA bus output sig-
nals since these outputs require 24 mA drivers. The
DVSS10 and DVSS12 pins provide the ground for the
internal digital logic. In addition, DVSS11 provides
ground for the internal digital and for the Input and
I/O pins.
The CMOS technology used in fabricating the
PCnet-ISA controller employs an n-type substrate. In
this technology, all V
DD
pins are electrically connected to
each other internally. Hence, in a 4-layer board, when
decoupling between V
DD
and critical V
SS
pins, the spe-
cific V
DD
pin that you connect to is not critical. In fact, the
V
DD
connection of the decoupling capacitor can be
made directly to the power plane, near the closest V
DD
pin to the V
SS
pin of interest. However, we recommend
that the V
SS
connection of the decoupling capacitor be
made directly to the V
SS
pin of interest as shown.
V
DD
Pin
V
SS
Pin
PCnet-ISA
via to V
DD
plane
via to V
SS
plane
AMD recommends that at least one low-frequency bulk
decoupling capacitor be used in the area of the
PCnet-ISA controller. 22
μ
F capacitors have worked
well for this. In addition, a total of 4 or 5 0.1
μ
F capaci-
tors have proven sufficient around the DV
SS
and DV
DD
pins that supply the drivers of the ISA bus output pins.
Analog Decoupling
The most critical pins are the analog supply and ground
pins. All of the analog supply and ground pins are lo-
cated in one corner of the device. Specific requirements
of the analog supply pins are listed below.
AVSS1 and AVDD3
These pins provide the power and ground for the
Twisted Pair and AUI drivers. Hence, they are very
noisy. A dedicated 0.1
μ
F capacitor between these pins
is recommended.
AVSS2 and AVDD2
These pins are the most critical pins on the PCnet-ISA
controller because they provide the power and ground
for the PLL portion of the chip. The VCO portion of the
PLL is sensitive to noise in the 60–200 kHz. range. To
prevent noise in this frequency range from disrupting the
VCO, AMD strongly recommends that the low-pass filter
shown below be implemented on these pins. Tests us-
ing this filter have shown significantly increased noise
immunity and reduced Bit Error Rate (BER) statistics in
designs using the PCnet-ISA controller.
相關(guān)PDF資料
PDF描述
AM79C960KC PCnetTM-ISA Single-Chip Ethernet Controller
AM79C960KCW PCnetTM-ISA Single-Chip Ethernet Controller
AM79C961AKCW PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
AM79C961AKC PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
AM79C961A PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C960KC 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:PCnetTM-ISA Single-Chip Ethernet Controller
AM79C960KC/W 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:LAN Node Controller
AM79C960KCW 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:PCnetTM-ISA Single-Chip Ethernet Controller
AM79C961 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Am79C961 - PCnet-ISA+ Jumperless Single-Chip Ethernet Controller for ISA
AM79C961/AM79C961A 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Using the Am79C961/Am79C961A (PCnet-ISA+/PCnet-ISA II) Survival Guide? 134KB (PDF)