參數(shù)資料
型號(hào): AM79C960
廠商: Advanced Micro Devices, Inc.
英文描述: PCnetTM-ISA Single-Chip Ethernet Controller
中文描述: PCnetTM -的ISA單芯片以太網(wǎng)控制器
文件頁(yè)數(shù): 26/127頁(yè)
文件大小: 814K
代理商: AM79C960
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P R E L I M I N A R Y
AMD
1-368
Am79C960
SD0-15
System Data Bus
This bus is used to transfer data to and from the PCnet-
ISA controller to system resources via the ISA data bus.
SD0-15 is driven by the PCnet-ISA controller when per-
forming slave read operations.
Input/Output
Likewise, the data on SD0-15 is latched by the
PCnet-ISA controller when performing slave write
operations.
Board Interface
ABOE
Address Buffer Output Enable Output
This pin goes LOW to enable an external octal buffer to
drive the contents of SA10-15 onto PRAB10-15. Only
six of the eight buffers are needed.
APCS
Address PROM Chip Select
This signal is asserted when the external Address
PROM is read. When an I/O read operation is per-
formed on the first 16 bytes in the PCnet-ISA controller’s
I/O space,
APCS
is asserted. The outputs of the exter-
nal Address PROM drive the PROM Data Bus. The
PCnet-ISA controller buffers the contents of the PROM
data bus and drives them on the lower eight bits of the
System Data Bus.
IOCS16
is not asserted during
this cycle.
Output
BPAM
Boot PROM Address Match
This pin indicates a Boot PROM access cycle. If no Boot
PROM is installed, this pin has a default value of HIGH
and thus may be left connected to V
DD
.
Input
BPCS
Boot PROM Chip Select
This signal is asserted when the Boot PROM is read. If
BPAM
is active and
MEMR
is active, the
BPCS
signal
will be asserted. The outputs of the external Boot
PROM drive the PROM Data Bus. The PCnet-ISA con-
troller buffers the contents of the PROM data bus and
drives them on the System Data Bus.
IOCS16
is not as-
serted during this cycle. If 16-bit cycles are performed, it
is the responsibility of external logic to assert
MEMCS16
signal.
Output
DXCVR
Disable Transceiver
This pin disables the transceiver. A high level indicates
the Twisted Pair Interface is active and the AUI interface
is inactive, or SLEEP mode has been entered. A low
level indicates the AUI interface is active and the
Twisted Pair interface is inactive.
Output
IOAM0-1
Input/Output Address Map
These inputs configure I/O address space for the
PCnet-ISA controller. The pins have an on-chip pullup
resistor and are pulled HIGH internally. The SA1-9 in-
puts are used for I/O address comparisons.
Input
IOAM1,0
I/O Base
0 0
300 Hex
0 1
320 Hex
1 0
340 Hex
1 1
360 Hex
LED0-3
LED Drivers
These pins sink 12 mA each for driving LEDs. Their
meaning is software configurable (see section ISA Bus
Configuration Registers) and they are active LOW.
Output
When EADI mode is selected, the pins named
LED1
,
LED2
, and
LED3
change in function while
LED0
contin-
ues to indicate 10BASE-T Link Status. The MAUSEL
input becomes the
EAR
input.
LED
EADI Function
1
SF/BD
2
SRD
3
SRDCLK
MAUSEL/
EAR
MAU Select/
External Address Reject
This pin selects the 10BASE-T MAU when HIGH and
the AUI interface when LOW if the XMAUSEL register
bit in ISACSR2 (ISA Configuration Register) is set. If the
XMAUSEL register bit is cleared, the MAUSEL pin is ig-
nored and the network interface is software selected.
This pin has a default value of HIGH if left unconnected.
Input
If EADI mode is selected, this pin becomes the
EAR
input. The incoming frame will be checked against the
internally active address detection mechanisms and the
result of this check will be OR’d with the value on the
EAR
pin. The
EAR
pin is defined as
REJECT
. See the
EADI section for details regarding the function and tim-
ing of this signal.
PRAB0-15
Private Address Bus
The Private Address Bus is the address bus used to
drive the Address PROM, Remote Boot PROM, and
SRAM. PRAB10-15 are required to be buffered by a Bus
Buffer with
ABOE
as its control and SA10-15 as its
inputs.
Input/Output
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