參數(shù)資料
型號： AM79C960
廠商： Advanced Micro Devices, Inc.
英文描述： PCnetTM-ISA Single-Chip Ethernet Controller
中文描述： PCnetTM -的ISA單芯片以太網(wǎng)控制器
文件頁數(shù)： 73/127頁
文件大小： 814K
代理商： AM79C960
P R E L I M I N A R Y
AMD
1-415
Am79C960
CSR96-97: Bus Interface Scratch Register 0
Bit
Name
Description
31-0
SCR0
This register is shared between
the Buffer Management Unit and
the Bus Interface Unit. All De-
scriptor Data communications
between the BIU and BMU are
written and read through SCR0
and SCR1 registers. The SCR0
register is undefined until written.
Read/write accessible only when
STOP bit is set.
CSR98-99: Bus Interface Scratch Register 1
Bit
Name
Description
31-0
SCR1
This register is shared between
the Buffer Management Unit and
the Bus Interface Unit. All De-
scriptor Data communications
between the BIU and BMU are
written and read through SCR0
and SCR1 registers.
Read/write accessible only when
STOP bit is set.
CSR104-105: SWAP
Bit
Name
Description
31-0
SWAP
This register performs word and
byte swapping depending upon if
32-bit or 16-bit internal write op-
erations are performed. This
register is used internally by the
BIU/BMU as a word or byte
swapper. The swap register can
perform 32-bit operations that
the PC can not; the register is ex-
ternally
accessible
reasons only. CSR104 holds the
lower 16 bits and CSR105 holds
the upper 16 bits.
The swap function is defined as
follows:
for
test
Internal Write
Operation
SWAP Register Result
→
SRC[15:0]
32-Bit word
SRC[31:16]
SWAP[15:0]
SWAP[31:16]
→
→
→
Lower 16-Bit
(CSR104)
SRC[15:8]
SRC[7:0]
SWAP[ 7: 0]
SWAP[15:8]
Read/write accessible only when
STOP bit is set.
CSR108-109: Buffer Management Scratch
Bit
Name
Description
31-0
BMSCR
The Buffer Management Scratch
register is used for assembling
Receive and Transmit Status.
This register is also used as the
primary scan register for Buffer
Management
BMSCR register is undefined un-
til written.
Read/write accessible only when
STOP bit is set.
Test
Modes.
CSR112: Missed Frame Count
Bit
Name
Description
15-0
MFC
Counts the number of missed
frames.
This register is always readable
and is cleared by STOP.
A write to this register performs
an increment when the ENTST
bit in CSR4 is set.
When MFC is all 1’s (65535) and
a missed frame occurs, MFC in-
crements to 0 and sets MFC0 bit
(CSR4.9).
CSR114: Receive Collision Count
Bit
Name
Description
15-0
RCVCC
Counts the number of Receive
collisions seen, regular and late.
This register is always readable
and is cleared by STOP.
A write to this register performs
an increment when the ENTST
bit in CSR4 is set.
When RCVCC is all 1’s (65535)
and a receive collision occurs,
RCVCC increments to 0 and sets
RCVCC0 bit (CSR4.5)
CSR124: Buffer Management Unit Test
Bit
Name
Description
This register is used to place the
BMU/BIU into various test modes
to support Test/Debug. This reg-
ister is writeable when the
ENTST bit in CSR4 is set.
相關PDF資料
PDF描述
AM79C960KC PCnetTM-ISA Single-Chip Ethernet Controller
AM79C960KCW PCnetTM-ISA Single-Chip Ethernet Controller
AM79C961AKCW PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
AM79C961AKC PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
AM79C961A PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
相關代理商/技術參數(shù)
參數(shù)描述
AM79C960KC 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-ISA Single-Chip Ethernet Controller
AM79C960KC/W 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller
AM79C960KCW 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-ISA Single-Chip Ethernet Controller
AM79C961 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Am79C961 - PCnet-ISA+ Jumperless Single-Chip Ethernet Controller for ISA
AM79C961/AM79C961A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Using the Am79C961/Am79C961A (PCnet-ISA+/PCnet-ISA II) Survival Guide? 134KB (PDF)
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