參數(shù)資料
型號： AM79C960
廠商： Advanced Micro Devices, Inc.
英文描述： PCnetTM-ISA Single-Chip Ethernet Controller
中文描述： PCnetTM -的ISA單芯片以太網(wǎng)控制器
文件頁數(shù)： 16/127頁
文件大小： 814K
代理商： AM79C960
P R E L I M I N A R Y
AMD
1-358
Am79C960
PIN DESCRIPTION: BUS MASTER MODE
These pins are part of the bus master mode. In order to
understand the pin descriptions, definition of some
terms from a draft of IEEE P996 are included.
IEEE P996 Terminology
Alternate Master
: Any device that can take control of
the bus through assertion of the
MASTER
signal. It has
the ability to generate addresses and bus control signals
in order to perform bus operations. All Alternate Mas-
ters must be 16 bit devices and drive
SBHE
.
Bus Ownership
: The Current Master possesses bus
ownership and can assert any bus control, address and
data lines.
Current Master
: The Permanent Master, Temporary
Master or Alternate Master which currently has owner-
ship of the bus.
Permanent Master
: Each P996 bus will have a device
known as the Permanent Master that provides certain
signals and bus control functions as described in Sec-
tion 3.5 (of the IEEE P996 spec), “Permanent Master”.
The Permanent Master function can reside on a Bus
Adapter or on the backplane itself.
Temporary Master
: A device that is capable of gener-
ating a DMA request to obtain control of the bus and
directly asserting only the memory and I/O strobes dur-
ing bus transfer. Addresses are generated by the DMA
device on the Permanent Master.
ISA Interface
AEN
Address Enable
This signal must be driven LOW when the bus performs
an I/O access to the device.
Input
DACK
DMA Acknowledge
Asserted LOW when the Permanent Master acknowl-
edges a DMA request. When
DACK
is asserted the
PCnet-ISA controller becomes the Current Master by
asserting the
MASTER
signal.
Input
DRQ
DMA Request
When the PCnet-ISA controller needs to perform a DMA
transfer, it asserts DRQ. The Permanent Master ac-
knowledges DRQ with assertion of
DACK
. When the
PCnet-ISA controller does not need the bus it deasserts
DRQ.
Output
IOCHRDY
I/O Channel Ready
When the PCnet-ISA controller is being accessed,
IOCHRDY HIGH indicates that valid data exists on the
Input/Output
data bus for reads and that data has been latched for
writes. When the PCnet-ISA controller is the Current
Master on the ISA bus, it extends the bus cycle as long
as IOCHRDY is LOW.
IOCS16
I/O Chip Select 16
When an I/O read or write operation is performed, the
PCnet-ISA controller will drive the
IOCS16
pin LOW to
indicate that the chip supports a 16-bit operation at this
address. (If the motherboard does not receive this sig-
nal, then the motherboard will convert a 16-bit access to
two 8-bit accesses.) The
IOCS16
pin is also an input and
must go HIGH at least once after reset for the PCnet-
ISA controller to perform 16-bit I/O operations. If this pin
is grounded then the PCnet-ISA controller only performs
8-bit I/O operations.
Input/Output
The PCnet-ISA controller follows the IEEE P996 specifi-
cation that recommends this function be implemented
as a pure decode of SA0-9 and AEN, with no depend-
ency on
SMEMR
,
MEMR
,
MEMW
,
IOR
, or
IOW
;
however, some PC/AT clone systems are not compat-
ible with this approach. For this reason, the PCnet-ISA
controller is recommended to be configured to run 8-bit
I/O on all machines. Since data is moved by memory cy-
cles there is virtually no performance loss incurred by
running 8-bit I/O and compatibility problems are virtually
eliminated. The PCnet-ISA controller can be configured
to run 8-bit-only I/O by disconnecting the
IOCS16
pin
from the ISA bus and tying the
IOCS16
pin to ground
instead.
IOR
I/O Read
IOR
is driven LOW by the host to indicate that an Input/
Output Read operation is taking place.
IOR
is only valid
if the AEN signal is LOW and the external address
matches the PCnet-ISA controller’s predefined I/O ad-
dress location. If valid,
IOR
indicates that a slave read
operation is to be performed.
Input
IOW
I/O Write
IOW
is driven LOW by the host to indicate that an Input/
Output Write operation is taking place.
IOW
is only valid
if AEN signal is LOW and the external address matches
the PCnet-ISA controller’s predefined I/O address loca-
tion. If valid,
IOW
indicates that a slave write operation
is to be performed.
Input
IRQ
Interrupt Request
An attention signal which indicates that one or more of
the following status flags is set: BABL, MISS, MERR,
RINT, IDON, RCVCCO, JAB, MFCO, or TXSTRT. All
status flags have a mask bit which allows for
suppression of INTR assertion. These flags have the fol-
lowing meaning:
Output
相關(guān)PDF資料
PDF描述
AM79C960KC PCnetTM-ISA Single-Chip Ethernet Controller
AM79C960KCW PCnetTM-ISA Single-Chip Ethernet Controller
AM79C961AKCW PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
AM79C961AKC PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C960KC 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-ISA Single-Chip Ethernet Controller
AM79C960KC/W 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller
AM79C960KCW 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-ISA Single-Chip Ethernet Controller
AM79C961 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Am79C961 - PCnet-ISA+ Jumperless Single-Chip Ethernet Controller for ISA
AM79C961/AM79C961A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Using the Am79C961/Am79C961A (PCnet-ISA+/PCnet-ISA II) Survival Guide? 134KB (PDF)
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