參數(shù)資料
型號(hào)： AM79C960
廠商： Advanced Micro Devices, Inc.
英文描述： PCnetTM-ISA Single-Chip Ethernet Controller
中文描述： PCnetTM -的ISA單芯片以太網(wǎng)控制器
文件頁(yè)數(shù)： 62/127頁(yè)
文件大小： 814K
代理商： AM79C960
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)當(dāng)前第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)
P R E L I M I N A R Y
AMD
1-404
Am79C960
4
DXMT2PD
Disable Transmit Two Part
Deferral. If DXMT2PD is set,
Transmit Two Part Deferral will
be disabled.
DXMT2PD is cleared by RESET
and is not affected by STOP.
Enable
Modified
Algorithm. If EMBA is set, a modi-
fied
back-off
implemented.
Read/Write accessible. EMBA is
cleared by RESET and is not af-
fected by STOP.
Reserved locations. Written as
zero and read as undefined.
3
EMBA
Back-off
algorithm
is
2-0
RES
CSR4: Test and Features Control
Bit
Name
Description
15
ENTST
Enable Test Mode operation.
When ENTST is set, writing to
test mode registers CSR124 and
CSR126 is allowed, and other
register test functions are en-
abled. In order to set ENTST, it
must be written with a “1” during
the first write access to CSR4
after RESET. Once a “0” is writ-
ten to this bit location, ENTST
cannot be set until after the
PCnet-ISA controller is reset.
ENTST is cleared by RESET.
When DMAPLUS = “1” , the burst
transaction counter in CSR80 is
disabled. If DMAPLUS = “0”, the
burst transaction counter is
enabled.
DMA-PLUS
is
RESET.
Timer Enable Register. If TIMER
is set, the Bus Timer Register,
CSR82, is enabled. If TIMER is
set, CSR82 must be written with
a value. If TIMER is cleared, the
Bus Timer Register is disabled.
TIMER is cleared by RESET.
Disable Transmit Polling. If
DPOLL is set, the Buffer Man-
agement
Unit
transmit polling. Likewise, if
DPOLL is cleared, automatic
transmit polling is enabled. If
DPOLL is set, TDMD bit in CSR0
must be periodically set in order
to initiate a manual poll of a trans-
mit descriptor. Transmit descrip-
tor polling will not take place if
TXON is reset.
14
DMAPLUS
cleared
by
13
TIMER
12
DPOLL
will
disable
DPOLL is cleared by RESET.
Auto Pad Transmit. When set,
APAD_XMT enables the auto-
matic padding feature. Transmit
frames will be padded to extend
them to 64 bytes, including FCS.
The FCS is calculated for the en-
tire frame (including pad) and
appended after the pad field.
APAD_XMT will override the pro-
gramming of the DXMTFCS bit
(CSR15.3).
APAD_ XMT is reset by activa-
tion of the RESET pin.
ASTRP_RCV enables the auto-
matic pad stripping feature. The
pad and FCS fields will be
stripped from receive frames and
not placed in the FIFO.
ASTRP_ RCV is reset by activa-
tion of the RESET pin.
Missed Frame Counter Overflow
Interrupt.
This bit indicates the MFC
(CSR112) has overflowed. Can
be cleared by writing a “1” to this
bit. Also cleared by RESET or
setting the STOP bit. Writing a “0”
has no effect.
Missed Frame Counter Overflow
Mask.
If MFCOM is set, MFCO will not
set INTR in CSR0.
MFCOM is set by Reset and is
not affected by STOP.
Reserved locations. Read and
written as zero.
Receive Collision Counter Over-
flow.
This bit indicates the Receive
Collision Counter (CSR114) has
overflowed. It can be cleared by
writing a 1 to this bit. Also cleared
by RESET or setting the STOP
bit. Writing a 0 has no effect.
Receive Collision Counter Over-
flow Mask.
If RCVCCOM is set, RCVCCO
will not set INTR in CSR0.
RCVCCOM is set by RESET and
is not affected by STOP.
Transmit Start status is set when-
ever PCnet-ISA controller begins
trans- mission of a frame.
When TXSTRT is set, IRQ is as-
serted if IENA = 1 and the mask
bit TXSTRTM (CSR4.2) is clear.
11
APAD_XMT
10 ASTRP_RCV
9
MFCO
8
MFCOM
7-6
RES
5
RCVCCO
4
RCVCCOM
3
TXSTRT
相關(guān)PDF資料
PDF描述
AM79C960KC PCnetTM-ISA Single-Chip Ethernet Controller
AM79C960KCW PCnetTM-ISA Single-Chip Ethernet Controller
AM79C961AKCW PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
AM79C961AKC PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
AM79C961A PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C960KC 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-ISA Single-Chip Ethernet Controller
AM79C960KC/W 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller
AM79C960KCW 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-ISA Single-Chip Ethernet Controller
AM79C961 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Am79C961 - PCnet-ISA+ Jumperless Single-Chip Ethernet Controller for ISA
AM79C961/AM79C961A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Using the Am79C961/Am79C961A (PCnet-ISA+/PCnet-ISA II) Survival Guide? 134KB (PDF)
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*