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參數(shù)資料
| 型號： | AM79C960 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnetTM-ISA Single-Chip Ethernet Controller |
| 中文描述： | PCnetTM -的ISA單芯片以太網(wǎng)控制器 |
| 文件頁數(shù)： | 45/127頁 |
| 文件大?。?/td> | 814K |
| 代理商： | AM79C960 |
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P R E L I M I N A R Y
AMD
1-387
Am79C960
EADI (External Address Detection
Interface)
This interface is provided to allow external address filter-
ing. It is selected by setting the EADISEL bit in
ISACSR2. This feature is typically utilized for terminal
servers, bridges and/or router type products. The use of
external logic is required to capture the serial bit stream
from the PCnet-ISA controller, compare it with a table of
stored addresses or identifiers, and perform the desired
function.
The EADI interface operates directly from the NRZ de-
coded data and clock recovered by the Manchester
decoder or input to the GPSI, allowing the external ad-
dress detection to be performed in parallel with frame
reception and address comparison in the MAC Station
Address Detection (SAD) block.
SRDCLK is provided to allow clocking of the receive bit
stream into the external address detection logic.
SRDCLK runs only during frame reception activity.
Once a received frame commences and data and clock
are available, the EADI logic will monitor the alternating
(“1,0”) preamble pattern until the two ones of the Start
Frame Delimiter (“1,0,1,0,1,0,1,1”) are detected, at
which point the SF/BD output will be driven HIGH.
After SF/BD is asserted the serial data from SRD should
be de-serialized and sent to a content addressable
memory (CAM) or other address detection device.
To allow simple serial to parallel conversion, SF/BD is
provided as a strobe and/or marker to indicate the de-
lineation of bytes, subsequent to the SFD. This provides
a mechanism to allow not only capture and/or decoding
of the physical or logical (group) address, it also facili-
tates the capture of header information to determine
protocol and or inter-networking information. The
EAR
pin is driven LOW by the external address comparison
logic to reject the frame.
If an internal address match is detected by comparison
with either the Physical or Logical Address field, the
frame will be accepted regardless of the condition of
EAR
. Incoming frames which do not pass the internal
address comparison will continue to be received. This
allows approximately 58 byte times after the last desti-
nation address bit is available to generate the
EAR
signal, assuming the device is not configured to accept
runt packets.
EAR
will be ignored after 64 byte times af-
ter the SFD, and the frame will be accepted if
EAR
has
not been asserted before this time. If Runt Packet Ac-
cept is configured, the
EAR
signal must be generated
prior to the receive message completion, which could be
as short as 12 byte times (assuming 6 bytes for source
address, 2 bytes for length, no data, 4 bytes for FCS) af-
ter the last bit of the destination address is available.
EAR
must have a pulse width of at least 200 ns.
Note that setting the PROM bit (CSR15, bit 15) will
cause all receive frames to be received, regardless of
the state of the
EAR
input.
If the DRCVPA bit (CSR15.13) is set and the logical
address (LADRF) is set to zero, only frames which are
not rejected by
EAR
will be received.
The EADI interface will operate as long as the STRT bit
in CSR0 is set, even if the receiver and/or transmitter
are disabled by software (DTX and DRX bits in CSR15
set). This situation is useful as a power down mode in
that the PCnet-ISA controller will not perform any DMA
operations; this saves power by not utilizing the ISA bus
driver circuits. However, external circuitry could still re-
spond to specific frames on the network to facilitate
remote node control.
The table below summarizes the operation of the EADI
features.
Table: Internal/External Address Recognition Capabilities
PROM
EAR
X
1
0
Required Timing
Received Messages
All Received Frames
All Received Frames
Physical/Logical Matches
1
0
0
No timing requirements
No timing requirements
Low for 200 ns within 512 bits after SFD
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C960KC | PCnetTM-ISA Single-Chip Ethernet Controller |
| AM79C960KCW | PCnetTM-ISA Single-Chip Ethernet Controller |
| AM79C961AKCW | PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C960KC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-ISA Single-Chip Ethernet Controller |
| AM79C960KC/W | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
| AM79C960KCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-ISA Single-Chip Ethernet Controller |
| AM79C961 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Am79C961 - PCnet-ISA+ Jumperless Single-Chip Ethernet Controller for ISA |
| AM79C961/AM79C961A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Using the Am79C961/Am79C961A (PCnet-ISA+/PCnet-ISA II) Survival Guide? 134KB (PDF) |
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