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參數(shù)資料
| 型號： | AM79C960 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnetTM-ISA Single-Chip Ethernet Controller |
| 中文描述： | PCnetTM -的ISA單芯片以太網(wǎng)控制器 |
| 文件頁數(shù)： | 17/127頁 |
| 文件大?。?/td> | 814K |
| 代理商： | AM79C960 |
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P R E L I M I N A R Y
AMD
1-359
Am79C960
BABL
Babble
RCVCCO
Receive Collision Count Overflow
JAB
Jabber
MISS
Missed Frame
MERR
Memory Error
MFCO
Missed Frame Count Overflow
RINT
Receive Interrupt
IDON
Initialization Done
TXSTRT
Transmit Start
LA17-23
Unlatched Address Bus
The unlatched address bus is driven by the PCnet-ISA
controller during bus master cycle.
Output
The functions of these unlatched address pins will
change when GPSI mode is invoked. The table below
shows the pin configuration in GPSI mode. Please refer
to the section on General Purpose Serial Interface for
detailed information on accessing this mode.
Pin
Pin Function in
Bus Master Mode
Pin Function in
GPSI Mode
Number
5
LA17
RXDAT
6
LA18
SRDCLK
7
LA19
RXCRS
9
LA20
CLSN
10
LA21
STDCLK
11
LA22
TXEN
12
LA23
TXDAT
MASTER
Master Mode
This signal indicates that the PCnet-ISA controller has
become the Current Master of the ISA bus. After the
PCnet-ISA controller has received a DMA Acknowledge
(
DACK
) in response to a DMA Request (DRQ), the
Ethernet controller asserts the
MASTER
signal to indi-
cate to the Permanent Master that the PCnet-ISA
controller is becoming the Current Master.
Output
MEMR
Memory Read
MEMR
goes LOW to perform a memory read operation.
Output
MEMW
Memory Write
MEMW
goes LOW to perform a memory write
operation.
Output
REF
Memory Refresh
When
REF
is asserted, a memory refresh is active. The
PCnet-ISA controller uses this signal to mask inadver-
tent DMA Acknowledge assertion during memory
Input
refresh periods. If
DACK
is asserted when
REF
is ac-
tive,
DACK
assertion is ignored.
REF
is monitored to
eliminate a bus arbitration problem observed on some
ISA platforms.
RESET
Reset
When RESET is asserted HIGH the PCnet-ISA control-
ler performs an internal system reset. RESET must be
held for a minimum of 10 XTAL1 periods before being
deasserted. While in a reset state, the PCnet-ISA con-
troller will tristate or deassert all outputs to predefined
reset levels. The PCnet-ISA controller resets itself upon
power-up.
Input
SA0-19
System Address Bus
This bus contains address information, which is stable
during a bus operation, regardless of the source.
SA17-19 contain the same values as the unlatched ad-
dress LA17-19. When the PCnet-ISA controller is the
Current Master, SA0-19 will be driven actively. When
the PCnet-ISA controller is not the Current Master, the
SA0-19 lines are continuously monitored to determine if
an address match exists for I/O slave transfers or Boot
PROM accesses.
Input/Output
SBHE
System Byte High Enable
This signal indicates the high byte of the system data
bus is to be used.
SBHE
is driven by the PCnet-ISA con-
troller when performing bus mastering operations.
Input/Output
SD0-15
System Data Bus
These pins are used to transfer data to and from the
PCnet-ISA controller to system resources via the ISA
data bus. SD0-15 is driven by the PCnet-ISA controller
when performing bus master writes and slave read op-
erations. Likewise, the data on SD0-15 is latched by the
PCnet-ISA controller when performing bus master
reads and slave write operations.
Input/Output
SMEMR
System Memory Read
This pin is used during Boot PROM access. The Boot
PROM can be disabled by not connecting this pin.
Input
Board Interface
APCS
Address PROM Chip Select
This signal is asserted when the external Address
PROM is read. When an I/O read operation is per-
formed on the first 16 bytes in the PCnet-ISA controller’s
I/O space,
APCS
is asserted. The outputs of the exter-
nal Address PROM drive the PROM Data Bus. The
PCnet-ISA controller buffers the contents of the PROM
data bus and drives them on the lower eight bits of the
System Data Bus.
Output
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C960KC | PCnetTM-ISA Single-Chip Ethernet Controller |
| AM79C960KCW | PCnetTM-ISA Single-Chip Ethernet Controller |
| AM79C961AKCW | PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| AM79C961AKC | PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| AM79C961A | PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C960KC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-ISA Single-Chip Ethernet Controller |
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| AM79C960KCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-ISA Single-Chip Ethernet Controller |
| AM79C961 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Am79C961 - PCnet-ISA+ Jumperless Single-Chip Ethernet Controller for ISA |
| AM79C961/AM79C961A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Using the Am79C961/Am79C961A (PCnet-ISA+/PCnet-ISA II) Survival Guide? 134KB (PDF) |
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