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參數(shù)資料
| 型號： | AM79C961AVCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 |
| 封裝： | TQFP-144 |
| 文件頁數(shù)： | 105/206頁 |
| 文件大小： | 1507K |
| 代理商： | AM79C961AVCW |
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Am79C961A
105
In loopback mode, this bit deter-
mines if the transmitter appends
FCS or if the receiver checks the
FCS.
This bit was called DTCR in the
LANCE (Am7990).
Read/write
accessible
when STOP or SPND bits are
set.
Loopback Enable allows PC-
net-ISA II controller to operate in
full duplex mode for test purpos-
es. When LOOP =
“
1", loopback
is enabled. In combination with
INTL and MENDECL, various
loopback modes are defined as
follows.
only
2
LOOP
Read/write
when STOP or SPND bits are
set. LOOP is cleared by RESET.
Disable Transmit. If this bit is set,
the PCnet-ISA II
controller will
not
access
Descriptor Ring and, therefore,
no transmissions will occur. DTX
=
“
0" will set TXON bit (CSR0.4)
after STRT (CSR0.1) is assert-
ed. DTX is defined after the ini-
tialization block is read.
Read/write
accessible
when STOP or SPND bits are
set.
Disable Receiver. If this bit is
set, the PCnet-ISA II controller
will not access the Receive
Descriptor Ring and, therefore,
all receive frame data are
ignored. DRX =
“
0" will set
RXON bit (CSR0.5) after STRT
(CSR0.1) is asserted. DRX is
defined after the initialization
block is read.
Read/write
accessible
when STOP or SPND bits are
set.
accessible
only
1
DTX
the
Transmit
only
0
DRX
only
CSR16: Initialization Block Address Lower
Bit
Name
Description
15-0
IADR
Lower 16 bits of the address of
the Initialization Block. Bit loca-
tion 0 must be zero. This register
is an alias of CSR1. Whenever
this register is written, CSR1 is
updated with CSR16
’
s contents.
Read/Write
accessible
when the STOP or SPND bits
are set. Unaffected by RESET.
only
CSR17: Initialization Block Address Upper
Bit
Name
Description
15-8
RES
Reserved locations. Written as
zero and read as undefined.
Upper 8 bits of the address of
the Initialization Block. Bit loca-
tions 15-8 must be written with
zeros. This register is an alias of
CSR2. Whenever this register is
written, CSR2 is updated with
CSR17
’
s contents.
Read/Write
accessible
when the STOP or SPND bits
are set. Unaffected by RESET.
7-0
IADR
only
CSR18-19: Current Receive Buffer Address
Bit
Name
Description
31-24
RES
Reserved locations. Written as
zero and read as undefined.
Contains the current receive
buffer address to which the PC-
net-ISA II controller will store in-
coming frame data.
Read/write accessible only when
STOP or SPND bits are set.
23-0
CRBA
CSR20-21: Current Transmit Buffer Address
Bit
Name
Description
31-24
RES
Reserved locations. Written as
zero and read as undefined.
Contains the current transmit
buffer address from which the
PCnet-ISA II controller is trans-
mitting.
Read/write accessible only when
STOP or SPND bits are set.
23-0
CXBA
LOOP
INTL
MENDECL
Loopback Mode
0
X
X
Non-loopback
1
0
X
External Loopback
1
1
0
Internal Loopback
Include MENDEC
1
1
1
Internal Loopback
Exclude MENDEC
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C961AVI | 制造商:Rochester Electronics LLC 功能描述: |
| AM79C961AVI/W | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
| AM79C961AVI\\W | 制造商:Rochester Electronics LLC 功能描述: |
| AM79C961AVI\W | 制造商:Rochester Electronics LLC 功能描述: |
| AM79C961AVIW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
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