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參數(shù)資料
| 型號： | AM79C961AVCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 |
| 封裝： | TQFP-144 |
| 文件頁數(shù)： | 72/206頁 |
| 文件大?。?/td> | 1507K |
| 代理商： | AM79C961AVCW |
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Am79C961A
8 bits, which are ignored), the entire packet will be
ignored. The MAC engine will wait for the network to go
inactive before attempting to receive the next packet.
Media Access Management
The basic requirement for all stations on the network is
to provide fairness of channel allocation. The 802.3/
Ethernet protocol defines a media access mechanism
which permits all stations to access the channel with
equality. Any node can attempt to contend for the chan-
nel by waiting for a predetermined time (Inter Packet
Gap interval) after the last activity, before transmitting
on the medium. The channel is a multidrop
communications medium (with various topological con-
figurations permitted) which allows a single station to
transmit and all other stations to receive. If two nodes
simultaneously contend for the channel, their signals
will interact, causing loss of data (defined as a collision).
It is the responsibility of the MAC to attempt to avoid
and recover from a collision, to guarantee data integrity
for the end-to-end transmission to the receiving station.
Medium Allocation (collision avoidance)
The IEEE 802.3 Standard (ISO/IEC 8802-3 1990)
requires that the CSMA/CD MAC monitor the medium
traffic by looking for carrier activity. When carrier is
detected the medium is considered busy, and the MAC
should defer to the existing message.
The IEEE 802.3 Standard also allows optional two part
deferral after a receive message.
See ANSI/IEEE Std 802.3-1990 Edition, 4.2.3.2.1:
“Note
:
It is possible for the PLS carrier sense
indication to fail to be asserted during a colli-
sion on the media. If the deference process
simply times the interpacket gap based on this
indication it is possible for a short interFrame
gap to be generated, leading to a potential re-
ception failure of a subsequent frame. To en-
hance system robustness the following option-
al measures, as specified in 4.2.8, are recom-
mended when InterFrameSpacingPart1 is
other than zero:
(1) Upon completing a transmission, start timing
the interpacket gap, as soon as transmitting
and carrier Sense are both false.
(2) When timing an interpacket gap following re-
ception, reset the interpacket gap timing if car-
rier Sense becomes true during the first 2/3 of
the interpacket gap timing interval. During the
final 1/3 of the interval the timer shall not be re-
set to ensure fair access to the medium. An ini-
tial period shorter than 2/3 of the interval is
permissible including zero.”
The MAC engine implements the optional receive two
part deferral algorithm, with a first part in-
ter-frame-spacing time of 6.0
μ
s. The second part of
the inter-frame-spacing interval is therefore 3.6
μ
s.
The PCnet-ISA II controller will perform the two-part
deferral algorithm as specified in Section 4.2.8 (Pro-
cess Deference). The Inter Packet Gap (IPG) timer will
start timing the 9.6
μ
s InterFrameSpacing after the
receive carrier is de-asserted. During the first part
deferral (InterFrameSpacingPart1
–
IFS1) the PC-
net-ISA II controller will defer any pending transmit
frame and respond to the receive message. The IPG
counter will be reset to zero continuously until the car-
rier de-asserts, at which point the IPG counter will
resume the 9.6
μ
s count once again. Once the IFS1
period of 6.0
μ
s has elapsed, the PCnet-ISA II control-
ler will begin timing the second part deferral
(InterFrameSpacingPart2
–
IFS2) of 3.6
μ
s. Once IFS1
has completed, and IFS2 has commenced, the PC-
net-ISA II controller will not defer to a receive packet if
a transmit packet is pending. This means that the PC-
net-ISA II controller will not attempt to receive the re-
ceive packet, since it will start to transmit, and generate
a collision at 9.6
μ
s. The PCnet-ISA II controller will
guarantee to complete the preamble (64-bit) and jam
(32-bit) sequence before ceasing transmission and
invoking the random backoff algorithm.
In addition, transmit two part deferral is implemented
as an option which can be disabled using the
DXMT2PD bit (CSR3). Two-part deferral after trans-
mission is useful for ensuring that severe IPG shrink-
age cannot occur in specific circumstances, causing a
transmit message to follow a receive message so
closely as to make them indistinguishable.
During the time period immediately after a transmission
has been completed, the external transceiver (in the
case of a standard AUI connected device), should gen-
erate the SQE Test message (a nominal 10 MHz burst
of 5-15 bit times duration) on the CI
±
pair (within 0.6
μ
s
–
1.6
μ
s after the transmission ceases). During the time
period in which the SQE Test message is expected the
PCnet-ISA II controller will not respond to receive car-
rier sense.
See ANSI/IEEE Std 802.3-1990 Edition, 7.2.4.6 (1):
“
At the conclusion of the output function, the
DTE opens a time window during which it ex-
pects to see the
signal_quality_erro
r signal as-
serted on the Control In circuit. The time win-
dow begins when the CARRIER_STATUS be-
comes CARRIER_OFF. If execution of the out-
put function does not cause CARRIER_ON to
occur, no SQE test occurs in the DTE. The du-
ration of the window shall be at least 4.0
μ
s but
no more than 8.0
μ
s. During the time window
the Carrier Sense Function is inhibited.
”
The PCnet-ISA II controller implements a carrier sense
“
blinding
”
period within 0
–
4.0
μ
s from de-assertion of
carrier sense after transmission. This effectively means
that when transmit two part deferral is enabled
(DXMT2PD is cleared) the IFS1 time is from 4
μ
s to 6
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C961AVI | 制造商:Rochester Electronics LLC 功能描述: |
| AM79C961AVI/W | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
| AM79C961AVI\\W | 制造商:Rochester Electronics LLC 功能描述: |
| AM79C961AVI\W | 制造商:Rochester Electronics LLC 功能描述: |
| AM79C961AVIW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
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