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參數(shù)資料
| 型號(hào)： | AM79C961AVCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 |
| 封裝： | TQFP-144 |
| 文件頁數(shù)： | 95/206頁 |
| 文件大?。?/td> | 1507K |
| 代理商： | AM79C961AVCW |
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Am79C961A
95
Refer to the section
“
ISA Bus Configuration Registers
”
for information on LED control via the ISACSRs.
MAGIC PACKET OPERATION
In the Magic Packet mode, PCnet-ISA II completes any
transmit and receive operations in progress, suspends
normal activity, and enters into a state where only a
Magic Packet could be detected. A Magic Packet frame
is a frame that contains a data sequence which repeats
the Physical Address (PADR[47:00]) at least sixteen
times frame sequentially, with bit[00] received first. In
Magic Packet suspend mode, the PCnet-ISA II remains
powered up. Slave accesses to the PCnet-ISA II are
still possible, the same as any other mode. All of the
received packets are flushed from the receive FIFO. An
LED and/or interrupt pin could be activated, indicating
the receive of a Magic Packet frame. This indication
could be used for a variety of management tasks.
Magic Packet Mode Activation
This mode can be enabled by either software or exter-
nal hardware means, but in either case, the MP_MODE
bit (CSR5, bit 1) must be set first.
Hardware Activation.
This is done by driving the
SLEEP pin low. Deasserting the SLEEP pin will return
the PCnet-ISA II to normal operation.
Software Activation.
This is done by setting the
MP_ENBL bit (CSR5, bit 2). Resetting this bit will return
the PCnet-ISA II to normal operation.
Magic Packet Receive Indicators
The reception of a Magic Packet can be indicated either
through one of the LEDs 1, 2 or 3, and/or the activation
of the interrupt pin. MP_INT bit (CSR5, bit 4) will also
be set upon the receive of the Magic Packet.
LED Indication
. Either one of the LEDs 1, 2, or 3 could
be activated by the receive of the Magic Packet. The
“
Magic Packet enable
”
bit (bit 9) in the ISACSR 5, 6 or
7 should be set to enable this feature. Note that the
polarity of the LED2 could be controlled by the
LEDXOR bit (ISACSR6, bit 14). The LED could be
deactivated by setting the STOP bit or resetting the
MP_ENBL bit (CSR5, bit 2).
Interrupt Indication
. Interrupt pin could be activated
by the receive of the Magic Packet. The MP_I_ENBL bit
(CSR5, bit 3) and IENA bit (CSR0, bit 6) should be set
to enable this feature.
Bit
Name
Description
1
MP_MODE
Magic Packet Mode.
Setting this bit is a prerequisite
for entering the Magic Packet
mode. It also redefines the
SLEEP pin to be a Magic Packet
enable pin. Read/Write accessi-
ble always. It is cleared by as-
serting the RESET pin, or read-
ing the RESET register.
Magic Packet Enable.
This bit when set, will force the
PCnet-ISA II into the Magic
Packet mode. Read/Write ac-
cessible always. It is cleared by
asserting the RESET pin or
reading the RESET register.
Magic Packet Interrupt Enable.
Acts as an unmask bit for the
MP_INT (CSR5, bit 4). Read/
Write accessible always. It is
cleared by asserting the RESET
pin or reading the RESET regis-
ter, or setting the STOP bit.
Magic Packet Receive Interrupt.
Will be set when a Magic Packet
has been received. Writing a
“
one
”
will clear this bit. It is
cleared by asserting the RESET
pin, or reading the RESET regis-
ter.
Magic Packet LED Enable.
When set, the LED output will be
asserted to indicate that a Magic
Packet has been received.
2
MP_ENBL
3
MP_I_ENBL
4
MP_INT
9
MP
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| AM79C961AVI | 制造商:Rochester Electronics LLC 功能描述: |
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| AM79C961AVIW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
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