參數(shù)資料
型號： AM79C961AVCW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
中文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝： TQFP-144
文件頁數(shù)： 99/206頁
文件大?。?/td> 1507K
代理商： AM79C961AVCW
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁當(dāng)前第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁
Am79C961A
99
When DXSUFLO is set to ZERO,
the transmitter is turned off when
an UFLO error occurs (CSR0,
TXON = 0).
When DXSUFLO is set to ONE,
the PCnet-ISA II controller
gracefully recovers from an
UFLO error. It scans the transmit
descriptor ring until it finds the
start of a new frame and starts a
new transmission.
Read/Write accessible always.
DXSUFLO is cleared by asserting
the RESET pin or reading the
Reset register and is not affected
by STOP.
Look Ahead Packet Processing
(LAPPEN). When set to a one,
the LAPPEN bit will cause the
PCnet-ISA II controller to gener-
ate an interrupt following the
descriptor write operation to the
first buffer of a receive packet.
This interrupt will be generated
in addition to the interrupt that is
generated following the descrip-
tor write operation to the last
buffer of a receive packet. The
interrupt will be signaled through
the RINT bit of CSR0.
Setting LAPPEN to a one also
enables the PCnet-ISA II con-
troller to read the STP bit of the
receive descriptors. PCnet-ISA
II controller will use STP infor-
mation to determine where it
should begin writing a receive
packet
’
s data. Note that while in
this mode, the PCnet-ISA II con-
troller can write intermediate
packet data to buffers whose
descriptors do not contain STP
bits set to one. Following the
write to the last descriptor used
by a packet, the PCnet-ISA II
controller will scan through the
next descriptor entries to locate
the next STP bit that is set to a
one. The PCnet-ISA II controller
will begin writing the next pack-
et
’
s data to the buffer pointed to
by that descriptor.
Note that because several
descriptors may be allocated by
the host for each packet, and not
all messages may need all of the
descriptors that are allocated
between descriptors that contain
STP = one, then some descrip-
tors/buffers may be skipped in
the ring. While performing the
5
LAPPEN
search for the next STP bit that
is set to one, the PCnet-ISA II
controller will advance through
the
receive
descriptor
regardless of the state of owner-
ship bits. If any of the entries that
are examined during this search
indicate OWN = one, PCnet-ISA
II will RESET the OWN bit to
zero in these entries. If a
scanned entry indicates host
ownership with STP=
“
0", then
the PCnet-ISA II controller will
not alter the entry, but will
advance to the next entry.
When the STP bit is found to be
true, but the descriptor that con-
tains this setting is not owned by
the PCnet-ISA II controller, then
the PCnet-ISA II controller will
stop advancing through the ring
entries and begin periodic poll-
ing of this entry. When the STP
bit is found to be true, and the
descriptor that contains this set-
ting is owned by the PCnet-ISA II
controller, then the PCnet-ISA II
controller will stop advancing
through the ring entries, store
the descriptor information that is
has just read, and wait for the
next receive to arrive.
This behavior allows the host
software to pre-assign buffer
space in such a manner that the
“
header
”
portion of a receive
packet will always be written to a
particular memory area, and the
“
data
”
portion of a receive pack-
et will always be written to a sep-
arate memory area. The inter-
rupt is generated when the
“
header
”
bytes have been writ-
ten to the
“
header
”
memory
area.
Read/Write accessible always.
The LAPPEN bit will be reset
zero
by
RESET
unaffected by the STOP. See
Appendix E for more information
on LAPP.
Disable Transmit Two Part
Deferral. (Described in the
Media
Access
section). If DXMT2PD is set,
Transmit Two Part Deferral will
be disabled.
DXMT2PD is cleared by RESET
and is not affected by STOP.
Enable Modified Back-off Algo-
rithm. If EMBA is set, a modified
ring
and
will
4
DXMT2PD
Management
3
EMBA
相關(guān)PDF資料
PDF描述
AM79C961AVIW PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
Am79C965A PCnet?-32 Single-Chip 32-Bit Ethernet Controller
AM79C970AKCW PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AKC PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C961AVI 制造商:Rochester Electronics LLC 功能描述:
AM79C961AVI/W 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller
AM79C961AVI\\W 制造商:Rochester Electronics LLC 功能描述:
AM79C961AVI\W 制造商:Rochester Electronics LLC 功能描述:
AM79C961AVIW 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*