94
Am79C961A
other option requires an external device (such as a
‘
loopback plug
’
) to loop the data back to the chip, a
function normally not available on a 10BASE-T
network.
The PCnet-ISA II chip has two dedicated FCS genera-
tors, eliminating the traditional LANCE limitations on
loopback FCS operation. The receive FCS generation
logic is always enabled. The transmit FCS generation
logic can be disabled (to emulate LANCE type loop-
back operation) by setting the DXMTFCS bit in the
Mode register (CSR15). In this configuration, software
must generate the FCS and append the four FCS bytes
to the transmit frame data.
The loopback facilities of the MAC Engine allow full
operation to be verified without disturbance to the net-
work. Loopback operation is also affected by the state
of the Loopback Control bits (LOOP, MENDECL, and
INTL) in CSR15. This affects whether the internal
MENDEC is considered part of the internal or external
loop- backpath.
The receive FCS generation logic in the PCnet-ISA II
chip is used for multicast address detection. Since this
FCS logic is always enabled, there are no restrictions
to the use of multicast addressing while in loopback
mode.
When performing an internal loopback, no frame will be
transmitted to the network. However, when the PC-
net-ISA II controller is configured for internal loopback
the receiver will not be able to detect network traffic.
External loopback tests will transmit frames onto the
network if the AUI port is selected, and the PCnet-ISA
II controller will receive network traffic while configured
for external loopback when the AUI port is selected.
Runt Packet Accept is automatically enabled when any
loopback mode is invoked.
Loopback mode can be performed with any frame size.
Runt Packet Accept is internally enabled (RPA bit in
CSR124 is not affected) when any loopback mode is
invoked. This is to be backwards compatible to the
LANCE (Am7990) software.
LEDs
The PCnet-ISA II controller
’
s LED control logic allows
programming of the status signals, which are displayed
on 3 LED outputs. One LED (LED0) is dedicated to dis-
playing 10BASE-T Link Status. The status signals
available are Collision, Jabber, Receive, Receive Polar-
ity, Transmit, Receive Address Match, and Full Duplex
Link Status. If more than one status signal is enabled,
they are ORed together. An optional pulse stretcher is
available for each programmable output. This allows
emulation of the TPEX (Am79C98) and TPEX
+
(Am79C100) LED outputs.
Each status signal is ANDed with its corresponding
enable signal. The enabled status signals run to a com-
mon OR gate:
The output from the OR gate is run through a pulse
stretcher, which consists of a 3-bit shift register clocked
at 38 Hz. The data input of the shift register is at logic
0. The OR gate output asynchronously sets all three
bits of the shift register when its output goes active. The
output of the shift register controls the associated LEDx
pin. Thus, the pulse stretcher provides an LED output
of 52 ms to 78 ms.
Signal
Behavior
COL
Active during collision activity on the network
FDLS
Active when Full Duplex operation is enabled
and functioning on the selected network port
JAB
Active when the PCnet-ISA II is jabbering on
the network
LNKST
Active during Link OK Not active during Link
Down
RCV
Active while receiving data
RVPOL
Active during receive polarity is OK Not active
during reverse receive polarity
RCVADDM
Active during Receive with Address Match
XMT
Active while transmitting data
AND
FDLS
FDLSE
AND
RCVM
RCVM E
AND
XMT
XMT E
AND
RVPOL
RVPOL E
AND
RCV
RCV E
AND
JAB
JAB E
AND
COL
COL E
OR
To
Pulse
Stretcher
AND
RCVADDM
RCVADDE
19364B-22
LED Control Logic