參數(shù)資料
型號(hào): AM79C961AVCW
廠(chǎng)商: ADVANCED MICRO DEVICES INC
元件分類(lèi): 微控制器/微處理器
英文描述: PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
中文描述: 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝: TQFP-144
文件頁(yè)數(shù): 98/206頁(yè)
文件大?。?/td> 1507K
代理商: AM79C961AVCW
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98
Am79C961A
TDMD is cleared by RESET or
by setting the STOP bit.
STOP assertion disables the
chip from all external activity.
The chip remains inactive until
either STRT or INIT are set. If
STOP, STRT and INIT are all set
together, STOP will override
STRT and INIT.
STOP is set by writing a
1" or by
RESET. Writing a
0" has no ef-
fect. STOP is cleared by setting
either STRT or INIT.
STRT assertion enables PCnet-
ISA II controller to send and
receive frames, and perform
buffer management operations.
Setting STRT clears the STOP
bit. If STRT and INIT are set to-
gether, PCnet-ISA II controller
initialization will be performed
first.
STRT is set by writing a
1". Writ-
ing a
0" has no effect. STRT is
cleared by RESET or by setting
the STOP bit.
INIT assertion enables PC-
net-ISA II controller to begin the
initialization procedure which
reads in the initialization block
from memory. Setting INIT
clears the STOP bit. If STRT and
INIT are set together, PCnet-ISA
II controller initialization will be
performed first. INIT is not
cleared when the initialization
sequence has completed.
INIT is set by writing a
1". Writ-
ing a
0" has no effect. INIT is
cleared by RESET or by setting
the STOP bit.
2
STOP
1
STRT
0
INIT
CSR1: IADR[15:0]
Bit
Name
Description
15-0 IADR [15:0]
Lower address of the Initializa-
tion address register. Bit location
0 must be zero. Whenever this
register is written, CSR16 is
updated with CSR1
s contents.
Read/Write
accessible
when the STOP or SPND bits
are set. Unaffected by RESET.
only
CSR2: IADR[23:16]
Bit
Name
Description
15-8
RES
Reserved locations. Read and
written as zero.
7-0 IADR [23:16]
Upper 8 bits of the address of
the Initialization Block. Bit loca-
tions 15-8 must be written with
zeros. Whenever this register is
written, CSR17 is updated with
CSR2
s contents.
Read/Write
accessible
when the STOP or SPND bits
are set. Unaffected by RESET.
only
CSR3: Interrupt Masks and Deferral Control
Bit
Name
Description
15
RES
Reserved location. Written as
zero and read as undefined.
Babble Mask. If BABLM is set,
the BABL bit in CSR0 will be
masked and will not set INTR
flag in CSR0.
BABLM is cleared by RESET
and is not affected by STOP.
Reserved location. Written as
zero and read as undefined.
Missed Frame Mask. If MISSM
is set, the MISS bit in CSR0 will
be masked and will not set INTR
flag in CSR0.
MISSM is cleared by RESET
and is not affected by STOP.
Memory Error Mask. If MERRM
is set, the MERR bit in CSR0 will
be masked and will not set INTR
flag in CSR0.
MERRM is cleared by RESET
and is not affected by STOP.
Receive
Interrupt
RINTM is set, the RINT bit in
CSR0 will be masked and will
not set INTR flag in CSR0.
RINTM is cleared by RESET
and is not affected by STOP.
Transmit Interrupt Mask. If
TINTM is set, the TINT bit in
CSR0 will be masked and will
not set INTR flag in CSR0.
TINTM is cleared by RESET and
is not affected by STOP.
Initialization Done Mask. If
IDONM is set, the IDON bit in
CSR0 will be masked and will
not set INTR flag in CSR0.
IDONM is cleared by RESET
and is not affected by STOP.
Reserved locations. Written as
zero and read as undefined.
Disable
Transmit
Underflow error.
14
BABLM
13
RES
12
MISSM
11
MERRM
10
RINTM
Mask.
If
9
TINTM
8
IDONM
7
RES
6
DXSUFLO
Stop
on
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