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| 型號(hào)： | AM79C978 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Single-Chip 1/10 Mbps PCI Home Networking Controller |
| 中文描述： | 單芯片的1 / 10 Mbps的家庭網(wǎng)絡(luò)控制器的PCI |
| 文件頁(yè)數(shù)： | 161/261頁(yè) |
| 文件大?。?/td> | 3803K |
| 代理商： | AM79C978 |
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Am79C978
161
Table 38.
EEDET Setting
1
ESK
EEPROM Serial Clock. This bit
and the EDI/EDO bit are used to
control host access to the EE-
PROM. Values programmed to
this bit are placed onto the EESK
pin at the rising edge of the next
clock following bit programming,
except when the PREAD bit is set
to 1 or the EEN bit is set to 0. If
both the ESK bit and the EDI/
EDO bit values are changed dur-
ing one BCR19 write operation,
while EEN = 1, then setup and
hold times of the EEDI pin value
with respect to the EESK signal
edge are not guaranteed.
ESK has no effect on the EESK
pin unless the PREAD bit is set to
0 and the EEN bit is set to 1.
This bit is read accessible al-
ways, write accessible only when
either the STOP or the SPND bit
is set. ESK is reset to 1 by
H_RESET and is not affected by
S_RESET or STOP.
0
EDI/EDO
EEPROM
Data Out. Data that is written to
Data
In/EEPROM
this bit will appear on the EEDI
output of the interface, except
when the PREAD bit is set to 1 or
the EEN bit is set to 0. Data that
is read from this bit reflects the
value of the EEDO input of the in-
terface.
EDI/EDO has no effect on the
EEDI pin unless the PREAD bit is
set to 0 and the EEN bit is set to
1.
Read accessible always; write
accessible only when either the
STOP or the SPND bit is set. EDI/
EDO is reset to 0 by H_RESET
and is not affected by S_RESET
or STOP.
BCR20: Software Style
This register is an alias of the location CSR58. Accesses
to and from this register are equivalent to accesses to
CSR58.
Bit
Name
Description
31-11 RES
Reserved locations. Written as
zeros and read as undefined.
EEDET Value
(BCR19[13])
EEPROM
Connected
Result if PREAD is Set to 1
EEPROM read operation is attempted.
Entire read sequence will occur, checksum
failure will result, PVALID is reset to 0.
EEPROM read operation is attempted.
Entire read sequence will occur, checksum
operation will pass, PVALID is set to 1.
EEPROM read operation is attempted.
Entire read sequence will occur, checksum
failure will result, PVALID is reset to 0.
EEPROM read operation is attempted.
Entire read sequence will occur, checksum
operation will pass, PVALID is set to 1.
Result of Automatic EEPROM Read
Operation Following H_RESET
First two EESK clock cycles are generated,
then EEPROM read operation is aborted
and PVALID is reset to 0.
First two EESK clock cycles are generated,
then EEPROM read operation is aborted
and PVALID is reset to 0.
EEPROM read operation is attempted.
Entire read sequence will occur, checksum
failure will result, PVALID is reset to 0.
EEPROM read operation is attempted.
Entire read sequence will occur, checksum
operation will pass, PVALID is set to 1.
0
No
0
Yes
1
No
1
Yes
Table 39.
Interface Pin Assignment
RST Pin
Low
High
PREAD or Auto
Read in Progress
X
1
EEN
X
X
EECS
0
Active
From ECS
Bit of BCR19
0
EESK
Tri-State
Active
From ESK Bit of
BCR19
LED1
EEDI
Tri-State
Active
From EEDI Bit of
BCR19
LED0
High
0
1
High
0
0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C978A | 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C978AKC\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C978AKC\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C978AKCW | 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller |
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