- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366551 > AM79C978 (Advanced Micro Devices, Inc.) Single-Chip 1/10 Mbps PCI Home Networking Controller PDF資料下載
參數(shù)資料
| 型號(hào)： | AM79C978 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Single-Chip 1/10 Mbps PCI Home Networking Controller |
| 中文描述： | 單芯片的1 / 10 Mbps的家庭網(wǎng)絡(luò)控制器的PCI |
| 文件頁數(shù)： | 33/261頁 |
| 文件大小： | 3803K |
| 代理商： | AM79C978 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁當(dāng)前第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁第231頁第232頁第233頁第234頁第235頁第236頁第237頁第238頁第239頁第240頁第241頁第242頁第243頁第244頁第245頁第246頁第247頁第248頁第249頁第250頁第251頁第252頁第253頁第254頁第255頁第256頁第257頁第258頁第259頁第260頁第261頁
Am79C978
33
BASIC FUNCTIONS
System Bus Interface
The Am79C978 controller is designed to operate as a
bus master during normal operations. Some slave I/O
accesses to the Am79C978 controller are required in
normal operations as well. Initialization of the
Am79C978 controller is achieved through a combina-
tion of PCI Configuration Space accesses, bus slave
accesses, bus master accesses, and an optional read
of a serial EEPROM that is performed by the
Am79C978 controller. The EEPROM read operation is
performed through the 93C46 EEPROM interface. The
ISO 8802-3 (IEEE/ANSI 802.3) Ethernet Address may
reside within the serial EEPROM. Some controller con-
figuration registers may also be programmed by the
EEPROM read operation.
The Address PROM, on-chip board-configuration reg-
isters, and the Ethernet controller registers occupy 32
bytes of address space. I/O and memory mapped I/O
accesses are supported. Base Address registers in the
PCI configuration space allow locating the address
space on a wide variety of starting addresses.
Software Interface
The software interface to the Am79C978 controller is
divided into three parts. One part is the PCI configura-
tion registers used to identify the Am79C978 controller
and to setup the configuration of the device. The setup
information includes the I/O or memory mapped I/O
base address, mapping of the Expansion ROM, and
the routing of the Am79C978 controller interrupt chan-
nel. This allows for a jumperless implementation.
The second portion of the software interface is the di-
rect access to the I/O resources of the Am79C978 con-
troller. The Am79C978 controller occupies 32 bytes of
address space that must begin on a 32-byte block
boundary. The address space can be mapped into I/O
or memory space (memory mapped I/O). The I/O Base
Address Register in the PCI Configuration Space con-
trols the start address of the address space if it is
mapped to I/O space. The Memory Mapped I/O Base
Address Register controls the start address of the ad-
dress space if it is mapped to memory space. The 32-
byte address space is used by the software to program
the Am79C978 controller operating mode, to enable
and disable various features, to monitor operating sta-
tus, and to request particular functions to be executed
by the Am79C978 controller.
The third portion of the software interface is the de-
scriptor and buffer areas that are shared between the
software and the Am79C978 controller during normal
network operations. The descriptor area boundaries
are set by the software and do not change during nor-
mal network operations. There is one descriptor area
for receive activity, and there is a separate area for
transmit activity. The descriptor space contains relocat-
able pointers to the network frame data, and it is used
to transfer frame status from the Am79C978 controller
to the software. The buffer areas are locations that hold
frame data for transmission or that accept frame data
that has been received.
Network Interfaces
The Am79C978 controller provides all of the PHY layer
functions for 10 Mbps (10BASE-T) or 1 Mbps. The
Am79C978 controller supports both half-duplex and
full-duplex operation on the network MII interface.
Media Independent Interface
The Am79C978 controller fully supports the MII ac-
cording to the IEEE 802.3u standard. This Reconcilia-
tion Sublayer interface allows a variety of PHYs
(100BASE-TX, 100BASE-FX, 100BASE-T4,
100BASE-T2, 10BASE-T, etc.) to be attached to the
Am79C978 device without future upgrade problems.
The MII interface is a 4-bit (nibble) wide data path inter-
face that runs at 25 MHz for 100-Mbps networks or 2.5
MHz for 10-Mbps networks. The interface consists of
two independent data paths, receive (RXD(3:0)) and
transmit (TXD(3:0)), control signals for each data path
(RX_ER, RX_DV, TX_EN), network status signals
(COL, CRS), clocks (RX_CLK, TX_CLK) for each data
path, and a two-wire management interface (MDC and
MDIO). See Figure 2.
MII Transmit Interface
The MII transmit clock is generated by the external
PHY and is sent to the Am79C978 controller on the
TX_CLK input pin. The clock can run at 25 MHz or 2.5
MHz, depending on the speed of the network to which
the external PHY is attached. The data is a nibble-wide
(4 bits) data path, TXD(3:0), from the Am79C978 con-
troller to the external PHY and is synchronous to the
rising edge of TX_CLK. The transmit process starts
when the Am79C978 controller asserts the TX_EN,
which indicates to the external PHY that the data on
TXD(3:0) is valid.
Normally, unrecoverable errors are signaled through
the MII to the external PHY with the TX_ER output pin.
The external PHY will respond to this error by generat-
ing a TX coding error on the current transmitted frame.
The Am79C978 controller does not use this method of
signaling errors on the transmit side. The Am79C978
controller will invert the FCS on the last byte generating
an invalid FCS. The TX_ER pin should be tied to GND.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C981 | Integrated Multiport Repeater Plus⑩ (IMR+⑩) |
| AM79C981JC | Integrated Multiport Repeater Plus⑩ (IMR+⑩) |
| AM79C982 | basic Integrated Multiport Repeater (bIMR) |
| AM79C982-4JC | basic Integrated Multiport Repeater (bIMR) |
| AM79C982-8JC | basic Integrated Multiport Repeater (bIMR) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C978A | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C978AKC\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C978AKC\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C978AKCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。