- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366551 > AM79C978 (Advanced Micro Devices, Inc.) Single-Chip 1/10 Mbps PCI Home Networking Controller PDF資料下載
參數(shù)資料
| 型號： | AM79C978 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Single-Chip 1/10 Mbps PCI Home Networking Controller |
| 中文描述： | 單芯片的1 / 10 Mbps的家庭網(wǎng)絡(luò)控制器的PCI |
| 文件頁數(shù)： | 242/261頁 |
| 文件大?。?/td> | 3803K |
| 代理商： | AM79C978 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁第231頁第232頁第233頁第234頁第235頁第236頁第237頁第238頁第239頁第240頁第241頁當前第242頁第243頁第244頁第245頁第246頁第247頁第248頁第249頁第250頁第251頁第252頁第253頁第254頁第255頁第256頁第257頁第258頁第259頁第260頁第261頁
B-2
Am79C978
Note:
The labels in the following text are used as ref-
erences in the timeline diagram that follows (Figure
B-1).
Setup
The driver should set up descriptors in groups of three,
with the OWN and STP bits of each set of three de-
scriptors to read as follows: 11b, 10b, 00b.
An option bit (LAPPEN) exists in CSR3, bit position 5;
the software should set this bit. When set, the LAPPEN
bit directs the controller to generate an INTERRUPT
when STP has been written to a receive descriptor by
the controller.
Flow
The controller polls the current receive descriptor at
some point in time before a message arrives. The con-
troller determines that this receive buffer is OWNed by
the controller and it stores the descriptor information to
be used when a message does arrive.
N0
Frame preamble appears on the wire, followed
by SFD and destination address.
N1
The 64th byte of frame data arrives from the
wire. This causes the controller to begin frame
data DMA operations to the first buffer.
C0
When the 64th byte of the message arrives,
the controller performs a lookahead operation
to the next receive descriptor. This descriptor
should be owned by the controller.
C1
The controller intermittently requests the bus
to transfer frame data to the first buffer as it ar-
rives on the wire.
S1
The driver remains idle.
C2
When the controller has completely filled the
first buffer, it writes status to the first descriptor.
C3
When the first descriptor for the frame has
been written, changing ownership from the
controller to the CPU, the controller will gener-
ate an SRP INTERRUPT. (This interrupt ap-
pears as a RINT interrupt in CSR0).
S1
The SRP INTERRUPT causes the CPU to
switch tasks to allow the controller
’
s driver to
run.
C4
During the CPU interrupt-generated task
switching, the controller is performing a looka-
head operation to the third descriptor. At this
point in time, the third descriptor is owned by
the CPU.
Note:
Even though the third buffer is not owned by the
controller, existing AMD Ethernet controllers will con-
tinue to perform data DMA into the buffer space that the
controller already owns (i.e., buffer number 2). The
controller does not know if buffer space in buffer num-
ber 2 will be sufficient or not for this frame, but it has no
way to tell except by trying to move the entire message
into that space. Only when the message does not fit will
it signal a buffer error condition--there is no need to
panic at this point that it discovers that it does not yet
own descriptor number 3.
S2
The first task of the drivers interrupt service
routing is to collect the header information
from the controller
’
s first buffer and pass it to
the application.
S3
The application will return an application buffer
pointer to the driver. The driver will add an off-
set to the application data buffer pointer, since
the controller will be placing the first portion of
the message into the first and second buffers.
(the modified application data buffer pointer
will only be directly used by the controller when
it reaches the third buffer.) The driver will place
the modified data buffer pointer into the final
descriptor of the group (#3) and will grant own-
ership of this descriptor to the controller.
C5
Interleaved with S2, S3, and S4 driver activity,
the controller will write frame data to buffer
number 2.
S4
The driver will next proceed to copy the con-
tents of the controller
’
s first buffer to the begin-
ning of the application space. This copy will be
to the exact (unmodified) buffer pointer that
was passed by the application.
S5
After copying all of the data from the first buffer
into the beginning of the application data
buffer, the driver will begin to poll the owner-
ship bit of the second descriptor. The driver is
waiting for the controller to finish filling the sec-
ond buffer.
C6
At this point, knowing that it had not previously
owned the third descriptor and knowing that
the current message has not ended (there is
more data in the FIFO), the controller will make
a last ditch lookahead to the final (third) de-
scriptor. This time the ownership will be TRUE
(i.e., the descriptor belongs tot he controller),
because the driver wrote the application
pointer into this descriptor and then changed
the ownership to give the descriptor to the con-
troller back at S3. Note that if steps S1, S2,
and S3 have not completed at this time, a
BUFF error will result.
C7
After filling the second buffer and performing
the last chance lookahead to the next descrip-
tor, the controller will write the status and
change the ownership bit of descriptor number
2.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C981 | Integrated Multiport Repeater Plus⑩ (IMR+⑩) |
| AM79C981JC | Integrated Multiport Repeater Plus⑩ (IMR+⑩) |
| AM79C982 | basic Integrated Multiport Repeater (bIMR) |
| AM79C982-4JC | basic Integrated Multiport Repeater (bIMR) |
| AM79C982-8JC | basic Integrated Multiport Repeater (bIMR) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C978A | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C978AKC\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C978AKC\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C978AKCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller |
發(fā)布緊急采購，3分鐘左右您將得到回復。