- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366551 > AM79C978 (Advanced Micro Devices, Inc.) Single-Chip 1/10 Mbps PCI Home Networking Controller PDF資料下載
參數(shù)資料
| 型號(hào)： | AM79C978 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Single-Chip 1/10 Mbps PCI Home Networking Controller |
| 中文描述： | 單芯片的1 / 10 Mbps的家庭網(wǎng)絡(luò)控制器的PCI |
| 文件頁(yè)數(shù)： | 63/261頁(yè) |
| 文件大?。?/td> | 3803K |
| 代理商： | AM79C978 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)當(dāng)前第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)第239頁(yè)第240頁(yè)第241頁(yè)第242頁(yè)第243頁(yè)第244頁(yè)第245頁(yè)第246頁(yè)第247頁(yè)第248頁(yè)第249頁(yè)第250頁(yè)第251頁(yè)第252頁(yè)第253頁(yè)第254頁(yè)第255頁(yè)第256頁(yè)第257頁(yè)第258頁(yè)第259頁(yè)第260頁(yè)第261頁(yè)
Am79C978
63
1. The controller does not own the current TDTE
and
TXDPOLL = 0 (CSR4, bit 12)
and
TXON = 1 (CSR0,
bit 4)
and
the poll time has elapsed,
or
2. The controller does not own the current TDTE
and
TXDPOLL = 0
and
TXON = 1
and
a frame has just
been received, or
3. The controller does not own the current TDTE
and
TXDPOLL = 0
and
TXON = 1
and
a frame has just
been transmitted.
Setting the TDMD bit of CSR0 will cause the microcode
controller to exit the poll counting code and immedi-
ately perform a polling operation. If RDTE ownership
has not been previously established, then an RDTE
poll will be performed ahead of the TDTE poll. If the mi-
crocode is not executing the poll counting code when
the TDMD bit is set, then the demanded poll of the
TDTE will be delayed until the microcode returns to the
poll counting code.
The user may change the poll time value from the de-
fault of 65,536 clock periods by modifying the value in
the Polling Interval register (CSR47).
Transmit Descriptor Table Entry
If, after a Transmit Descriptor Table Entry (TDTE) ac-
cess, the Am79C978 controller finds that the OWN bit
of that TDTE is not set, the Am79C978 controller re-
sumes the poll time count and re-examines the same
TDTE at the next expiration of the poll time count.
If the OWN bit of the TDTE is set, but the Start of
Packet (STP) bit is not set, the Am79C978 controller
will immediately request the bus in order to clear the
OWN bit of this descriptor. (This condition would nor-
mally be found following a late collision (LCOL) or retry
(RTRY) error that occurred in the middle of a transmit
frame chain of buffers.) After resetting the OWN bit of
this descriptor, the Am79C978 controller will again im-
mediately request the bus in order to access the next
TDTE location in the ring.
If the OWN bit is set and the buffer length is 0, the OWN
bit will be cleared. In the C-LANCE device, the buffer
length of 0 is interpreted as a 4096-byte buffer. A zero
length buffer is acceptable as long as it is not the last
buffer in a chain (STP = 0 and ENP = 1).
If the OWN bit and STP are set, then microcode control
proceeds to a routine that will enable transmit data
transfers to the FIFO. TheAm79C978 controller will
look ahead to the next transmit descriptor after it has
performed at least one transmit data transfer from the
first buffer.
If the Am79C978 controller does not own the next
TDTE (i.e., the second TDTE for this frame), it will com-
plete transmission of the current buffer and update the
status of the current (first) TDTE with the BUFF and
UFLO bits being set. If DXSUFLO (CSR3, bit 6) is
cleared to 0, the underflow error will cause the trans-
mitter to be disabled (CSR0, TXON = 0).
TheAm79C978 controller will have to be re-initialized to
restore the transmit function. Setting DXSUFLO to 1
enables the Am79C978 controller to gracefully recover
from an underflow error. The device will scan the trans-
mit descriptor ring until it finds either the start of a new
frame or a TDTE it does not own. To avoid an underflow
situation in a chained buffer transmission, the system
should always set the transmit chain descriptor own
bits in reverse order.
If the Am79C978 controller does own the second TDTE
in a chain, it will gradually empty the contents of the first
buffer (as the bytes are needed by the transmit opera-
tion), perform a single-cycle DMA transfer to update
the status of the first descriptor (clear the OWN bit in
TMD1), and then it may perform one data DMA access
on the second buffer in the chain before executing an-
other lookahead operation. (i.e., a lookahead to the
third descriptor.)
It is imperative that the host system never reads the
TDTE OWN bits out of order. TheAm79C978 controller
normally clears OWN bits in strict FIFO order. How-
ever, the Am79C978 controller can queue up to two
frames in the transmit FIFO. When the second frame
uses buffer chaining, the Am79C978 controller might
return ownership out of normal FIFO order. The OWN
bit for the last (and maybe only) buffer of the first frame
is not cleared until transmission is completed. During
the transmission the Am79C978 controller will read in
buffers for the next frame and clear their OWN bits for
all but the last one. The first and all intermediate buffers
of the second frame can have their OWN bits cleared
before the Am79C978 controller returns ownership for
the last buffer of the first frame.
If an error occurs in the transmission before all of the
bytes of the current buffer have been transferred,
transmit status of the current buffer will be immediately
updated. If the buffer does not contain the end of
packet, the Am79C978 controller will skip over the rest
of the frame which experienced the error. This is done
by returning to the polling microcode where the
Am79C978 controller will clear the OWN bit for all de-
scriptors with OWN = 1 and STP = 0 and continue in
like manner until a descriptor with OWN = 0 (no more
transmit frames in the ring) or OWN = 1 and STP = 1
(the first buffer of a new frame) is reached.
At the end of any transmit operation, whether success-
ful or with errors, immediately following the completion
of the descriptor updates, the Am79C978 controller will
always perform another polling operation. As described
earlier, this polling operation will begin with a check of
the current RDTE, unless the Am79C978 controller al-
ready owns that descriptor. Then the Am79C978 con-
troller will poll the next TDTE. If the transmit descriptor
OWN bit has a 0 value, the Am79C978 controller will
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C981 | Integrated Multiport Repeater Plus⑩ (IMR+⑩) |
| AM79C981JC | Integrated Multiport Repeater Plus⑩ (IMR+⑩) |
| AM79C982 | basic Integrated Multiport Repeater (bIMR) |
| AM79C982-4JC | basic Integrated Multiport Repeater (bIMR) |
| AM79C982-8JC | basic Integrated Multiport Repeater (bIMR) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C978A | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C978AKC\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C978AKC\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C978AKCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。