參數(shù)資料
型號(hào)： AM79C978AKCW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： Single-Chip 1/10 Mbps PCI Home Networking Controller
中文描述： 5 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP160
封裝： PLASTIC, QFP-160
文件頁(yè)數(shù)： 116/256頁(yè)
文件大?。?/td> 3505K
代理商： AM79C978AKCW
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116
Am79C978A
by H_RESET or S_RESET and is
unaffected by the STOP bit.
9
MFCO
Missed Frame Counter Overflow is
set by the Am79C978A controller
when the Missed Frame Counter
(CSR112
and
wrapped around.
CSR113)
has
When MFCO is set, INTA is as-
serted if IENA is 1 and the mask
bit MFCOM is 0.
This bit is always read/write ac-
cessible. MFCO is cleared by the
host by writing a 1. Writing a 0
has no effect. MFCO is cleared
by H_RESET, S_RESET, or by
setting the STOP bit.
8
MFCOM
Missed Frame Counter Overflow
Mask. If MFCOM is set, the MFCO
bit will be masked and unable to
set the INTR bit.
This bit is always read/write ac-
cessible. MFCOM is set to 1 by
H_RESET or S_RESET and is
not affected by the STOP bit.
7
UINTCMD
User
UINTCMD can be used by the
host to generate an interrupt un-
related to any network activity.
When UINTCMD is set, INTA is
asserted if IENA is set to 1. Write
a 1 to UINT to clear UINTCMD
and stop interrupts.
Interrupt
Command.
This bit is always read/write ac-
cessible. UINTCMD is cleared by
H_RESET or S_RESET or by
setting the STOP bit.
6
UINT
User Interrupt. UINT is set by the
Am79C978A controller after the
host has issued a user interrupt
command by setting UINTCMD
(CSR4, bit 7) to 1.
This bit is always read/write ac-
cessible. UINT is cleared by the
host by writing a 1. Writing a 0
has no effect. UINT is cleared by
H_RESET or S_RESET or by
setting the STOP bit.
5
RCVCCO
Receive Collision Counter Over-
flow is set by the Am79C978A
controller when the Receive Col-
lision Counter (CSR114 and
CSR115) has wrapped around.
When RCVCCO is set, INTA is
asserted if IENA is 1 and the
mask bit RCVCCOM is 0.
This bit is always read/write ac-
cessible. RCVCCO is cleared by
the host by writing a 1. Writing a
0 has no effect. RCVCCO is
cleared
by
S_RESET, or by setting the
STOP bit.
H_RESET,
4
RCVCCOM Receive Collision Counter Over-
flow Mask. If RCVCCOM is set,
the RCVCCO bit will be masked
and unable to set the INTR bit.
This bit is always read/write ac-
cessible. RCVCCOM is set to 1
by H_RESET or S_RESET and is
not affected by the STOP bit.
3
TXSTRT
Transmit Start status is set by the
Am79C978A controller whenever
it begins transmission of a frame.
When TXSTRT is set, INTA is as-
serted if IENA is 1 and the mask
bit TXSTRTM is 0.
This bit is always read/write ac-
cessible. TXSTRT is cleared by
the host by writing a 1. Writing a 0
has no effect. TXSTRT is cleared
by H_RESET, S_RESET, or by
setting the STOP bit.
2
TXSTRTM Transmit
Start
Mask.
If
TXSTRTM is set, the TXSTRT
bit will be masked and unable
to set the INTR bit.
This bit is always read/write ac-
cessible. TXSTRTM is set to 1
by H_RESET or S_RESET and
is not affected by the STOP bit.
1-0
RES
Reserved locations. Written as
zeros and read as undefined.
CSR5: Extended Control and Interrupt 1
Certain bits in CSR5 indicate the cause of an interrupt.
The register is designed so that these indicator bits are
cleared by writing ones to those bit locations. This
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C978AVCW 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller
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AM79C978VC/W 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller
AM79C979BKC\\W 制造商:Advanced Micro Devices 功能描述:
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