160
Am79C978A
1
ESK
EEPROM Serial Clock. This bit and
the EDI/EDO bit are used to control
host access to the EEPROM. Val-
ues programmed to this bit are
placed onto the EESK pin at the ris-
ing edge of the next clock following
bit programming, except when the
PREAD bit is set to 1 or the EEN bit
is set to 0. If both the ESK bit and
the EDI/EDO bit values are
changed during one BCR19 write
operation, while EEN = 1, then set-
up and hold times of the EEDI pin
value with respect to the EESK sig-
nal edge are not guaranteed.
ESK has no effect on the EESK
pin unless the PREAD bit is set to
0 and the EEN bit is set to 1.
This bit is read accessible al-
ways, write accessible only when
either the STOP or the SPND bit
is set. ESK is reset to 1 by
H_RESET and is not affected by
S_RESET or STOP.
0
EDI/EDO
EEPROM
Data Out. Data that is written to
this bit will appear on the EEDI
output of the interface, except
when the PREAD bit is set to 1 or
the EEN bit is set to 0. Data that
is read from this bit reflects the
value of the EEDO input of the
interface.
Data
In/EEPROM
EDI/EDO has no effect on the
EEDI pin unless the PREAD bit
is set to 0 and the EEN bit is set
to 1.
Read accessible always; write
accessible only when either the
STOP or the SPND bit is set. EDI/
EDO is reset to 0 by H_RESET
and is not affected by S_RESET
or STOP.
BCR20: Software Style
This register is an alias of the location CSR58. Accesses
to and from this register are equivalent to accesses to
CSR58.
Bit
Name
Description
31-11 RES
Reserved locations. Written as
zeros and read as undefined.
10
APERREN
Advanced Parity Error Handling
Enable. When APERREN is set
to 1, the BPE bits (RMD1 and
TMD1, bit 23) start having a
meaning. BPE will be set in the
descriptor associated with the
buffer that was accessed when a
data parity error occurred. Note
that since the advanced parity er-
ror handling uses an additional bit
in the descriptor, SWSTYLE (bits
7-0 of this register) must be set to
2
or
3
to
Am79C978A controller to use 32-
bit software structures.
program
the
APERREN does not affect the re-
porting of address parity errors or
data parity errors that occur when
the Am79C978A controller is the
target of the transfer.
Read anytime; write accessible
only when either the STOP or the
SPND bit is set. APERREN is
cleared by H_RESET and is not
affected by S_RESET or STOP.
9
RES
Reserved location. Written as zero;
read as undefined.
8
SSIZE32
Software Size 32 bits. When set,
this
bit
indicates
Am79C978A controller utilizes
32-bit software structures for the
initialization block and the trans-
mit and receive descriptor en-
tries. When cleared, this bit
indicates that the Am79C978A
controller utilizes 16-bit software
structures for the initialization
block and the transmit and re-
ceive descriptor entries. In this
mode, the Am79C978A controller
is backwards compatible with the
Am7990 LANCE and Am79C960
PCnet-ISA controllers.
that
the
The value of SSIZE32 is deter-
mined by the Am79C978A con-
troller according to the setting of
the Software Style (SWSTYLE,
bits 7-0 of this register).
This bit is always read accessible.
SSIZE32 is read only; write opera-
tions will be ignored. SSIZE32 will
be cleared after H_RESET (since
SWSTYLE defaults to 0) and is