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參數(shù)資料
| 型號(hào)： | AM79C978AKCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Single-Chip 1/10 Mbps PCI Home Networking Controller |
| 中文描述： | 5 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 65/256頁(yè) |
| 文件大?。?/td> | 3505K |
| 代理商： | AM79C978AKCW |
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Am79C978A
65
causing a transmit message to follow a receive mes-
sage so closely as to make them indistinguishable.
During the time period immediately after a transmis-
sion has been completed, the external transceiver
should generate the SQE Test message within 0.6 to
1.6 ms after the transmission ceases. During the time
period in which the SQE Test message is expected,
the Am79C978A controller will not respond to receive
carrier sense.
See ANSI/IEEE Std 802.3-1993 Edition, 7.2.4.6 (1):
“
At the conclusion of the output function, the DTE
opens a time window during which it expects to see
the signal_quality_error signal asserted on the Con-
trol In circuit. The time window begins when the
CARRIER_STATUS becomes CARRIER_OFF. If
execution of the output function does not cause
CARRIER_ON to occur, no SQE test occurs in the
DTE. The duration of the window shall be at least 4.0
μ
s but no more than 8.0
μ
s. During the time window
the Carrier Sense Function is inhibited.
”
The Am79C978A controller implements a carrier
sense
“
blinding
”
period of 4.0
μ
s length starting from
the deassertion of carrier sense after transmission.
This effectively means that when transmit two-part de-
ferral is enabled (DXMT2PD is cleared), the IFS1 time
is from 4 ms to 6 ms after a transmission. However,
since IPG shrinkage below 4 ms will rarely be encoun-
tered on a correctly configured network, and since the
fragment size will be larger than the 4 ms blinding win-
dow, the IPG counter will be reset by a worst case IPG
shrinkage/fragment scenario and the Am79C978A
controller will defer its transmission. If carrier is de-
tected within the 4.0 to 6.0 ms IFS1 period, the
Am79C978A controller will not restart the
“
blinding
”
period, but only restart IFS1.
Collision Handling
Collision detection is performed and reported to the
MAC engine via the COL input pin.
If a collision is detected before the complete preamble/
SFD sequence has been transmitted, the MAC engine
will complete the preamble/SFD before appending the
jam sequence. If a collision is detected after the pream-
ble/SFD has been completed, but prior to 512 bits
being transmitted, the MAC engine will abort the trans-
mission and append the jam sequence immediately.
The jam sequence is a 32-bit all zeros pattern.
The MAC engine will attempt to transmit a frame a total of 16
times (initial attempt plus 15 retries) due to normal collisions
(those within the slot time). Detection of collision will cause
the transmission to be rescheduled to a time determined by
the random backoff algorithm. If a single retry was required,
the 1 bit will be set in the transmit frame status. If more than
one retry was required, the MORE bit will be set. If all 16 at-
tempts experienced collisions, the RTRY bit will be set (1
and MORE will be clear), and the transmit message will be
flushed from the FIFO. If retries have been disabled by set-
ting the DRTY bit in CSR15, the MAC engine will abandon
transmission of the frame on detection of the first collision. In
this case, only the RTRY bit will be set, and the transmit mes-
sage will be flushed from the FIFO.
If a collision is detected after 512 bit times have been
transmitted, the collision is termed a late collision. The
MAC engine will abort the transmission, append the
jam sequence, and set the LCOL bit. No retry attempt
will be scheduled on detection of a late collision, and
the transmit message will be flushed from the FIFO.
The ISO 8802-3 (IEEE/ANSI 802.3) Standard requires
use of a
“
truncated binary exponential backoff
”
algo-
rithm, which provides a controlled pseudo random
mechanism to enforce the collision backoff interval,
before retransmission is attempted.
See ANSI/IEEE Std 802.3-1990 Edition, 4.2.3.2.5:
“
At the end of enforcing a collision (jamming), the
CSMA/CD sublayer delays before attempting to re-
transmit the frame. The delay is an integer multiple
of slot time. The number of slot times to delay be-
fore the nth retransmission attempt is chosen as a
uniformly distributed random integer r in the range:
0
≤
r < 2k Where k = Min (N,10).
”
TheAm79C978A controller provides an alternative al-
gorithm, which suspends the counting of the slot time/
IPG during the time that receive carrier sense is de-
tected. This aids in networks where large numbers of
nodes are present, and numerous nodes can be in col-
lision. It effectively accelerates the increase in the
backoff time in busy networks and allows nodes not in-
volved in the collision to access the channel, while the
colliding nodes await a reduction in channel activity.
Once channel activity is reduced, the nodes resolving
the collision time-out their slot time counters as normal.
This modified backoff algorithm is enabled when EMBA
(CSR3, bit 3) is set to 1.
Transmit Operation
The transmit operation and features of the
Am79C978A controller are controlled by programma-
ble options. TheAm79C978A controller offers a large
transmit FIFO to provide frame buffering for increased
system latency, automatic retransmission with no FIFO
reload, and automatic transmit padding.
Transmit Function Programming
Automatic transmit features such as retry on colli-
sion, FCS generation/transmission, and pad field in-
sertion can all be programmed to provide flexibility in
the (re-) transmission of messages.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C978AVCW | Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C978 | Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C981 | Integrated Multiport Repeater Plus⑩ (IMR+⑩) |
| AM79C981JC | Integrated Multiport Repeater Plus⑩ (IMR+⑩) |
| AM79C982 | basic Integrated Multiport Repeater (bIMR) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C978AVCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C978KC/W | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C978VC/W | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C979BKC\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C98 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Twisted-Pair Ethernet Transceiver (TPEX) |
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