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C165UTAH
USB Interface Controller
Data Sheet
343
2001-02-23
15.7.2
In-Transfer (Transmit)
An In-transfer means that the device will send data to the host by using endpointX. This
transfer is started by a bulk_in, interrupt, control_in or iso_in request from the host.
SW sets up source-pointer (to a memory-block containing the data to be sent), a
destination-pointer
(usbd_txwr-registerX)
maxpacketlength) of the EPEC for the endpoint on which the transfer is to be done;
the packetlength must always be the maxpacketlength for this endpoint for interrupt-,
bulk_in or control_in-transfers except for the last packet to be transferred, for
isochronous_in-endpoints this endpoint must be according to the sequence of
packetlengths and the data which is available to be sent.
If SW wants to send a packet of zero bytes, it must not use the EPEC, but must write
‘1’ to the corresponding usbd_tx_eod-register of the USB
SW writes EPEC-start, EPEC transferres the data from the memory to the USB-fifoX;
when host requests for the data, it is transferred through the fifo to the host; each time,
the USB-block has space in the fifo and may accept a write into the usbd_txwr-
register, the udc_txwr-interrupt is generated (for normal functionality this can be
ignored as the EPEC uses this as a handshake for the next transfer)
when EPEC has transferred all the data, it generates the EPEC-interrupt; SW must
read the EPEC-interrupt-register and clear the (to the endpoint) corresponding bit by
writing a ‘1’ to it
when the transfer over the USB is finished, the udc_tx_done-interruptX is generated
and SW can check the corresponding bit in the Status-Register, wheather the transfer
was successful or not; this is for bulk, interrupt and control-Endpoints only, not for
Isochonous Endpoints (where no ACK will be sent as Handshake)
for non-Iso-transfers: if fhe transfer was ACK’d, the next packet can be set up for
transmission, otherwise, host expects the same data to be resent
SW must set up again the EPEC source-, destination-pointer and packetlength and
start the transfer
and
the
packetlenght
(usually
If SW has already set up data in a tx-fifo and now, e.g. host changes the configuration
or interfaces, SW can use a write into the command-register to flush the fifo of the
corresponding endpoint. Before doing this, the EPEC-channel must be disabled or
reprorgammed, otherwise the next pending bytes will be transferred into the tx-fifo.
15.7.3
Out-Transfer (Receive)
During an Out-transfer, host is transferring data to the device. SW must provide an free
memory-block for each endpoint and set up the EPEC for moving arriving data from the
USB-block to a free memory-location.
SW provides an free memory-block and sets up source- (usbd_rxrr-registerX),
destination-pointer (free memory-block) and packet lenght of the EPEC and sets the
TXR_ENAx bit (refer to Table 20, “EPEC_CTRL_REGx Source Pointer Register,” on