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C165UTAH
System Reset
Data Sheet
439
2001-02-23
19
System Reset
The internal system reset function provides initialization of the C165UTAH into a defined
default state and is invoked either by asserting a hardware reset signal on pin RSTIN
(Hardware Reset Input), upon the execution of the SRST instruction (Software Reset) or
by an overflow of the watchdog timer (WDT).
Whenever one of these conditions occurs, the microcontroller is reset into its predefined
default state through an internal reset procedure. When a reset is initiated, pending
internal hold states are cancelled and the current internal access cycle (if any) is
completed. An external bus cycle is aborted, except for a watchdog reset (see
description). After that the bus pin drivers and the I/O pin drivers are switched off
(tristate). RSTOUT is activated depending on the reset source.
The internal reset procedure requires 516 CPU clock cycles in order to perform a
complete reset sequence. This 516 cycle reset sequence is started upon a watchdog
timer overflow, a SRST instruction or when the reset input signal RSTIN is latched low
(hardware reset). The internal reset condition is active at least for the duration of the
reset sequence and then until the RSTIN input is inactive. When this internal reset
condition is removed (reset sequence complete and RSTIN inactive), the reset
configuration is latched from PORT0, and pins ALE, RD and WR are driven to their
inactive levels.
Note:
Bit ADP, which selects the Adapt mode during low RSTIN signal, is latched with
the rising edge of RSTIN.
After the internal reset condition is removed, the microcontroller will start program
execution from memory location 00’0000
H
in code segment zero. This start location will
typically hold a branch instruction to the start of a software initialization routine for the
application specific configuration of peripherals and CPU Special Function Registers.