
C165UTAH
IOM-2 Interface Controller
Data Sheet
375
2001-02-23
A comparison is performed on the first byte after the opening flag with SAP1, SAP2 and
“group” SAPI (FE
H
/FC
H
). In the case of a match, all following bytes are stored in RFIFO.
16.7.1.4
Transparent Mode 2 (MDS2-0 = ’101’).
Characteristics:
A comparison is performed only on the second byte after the opening flag, with TEI1,
TEI2 and group TEI (FF
H
). In case of a match the rest of the frame is stored in the RFIFO.
TEI recognition
16.7.1.5
Extended Transparent Mode (MDS2-0 = ’100’).
Characteristics:
In extended transparent mode fully transparent data transmission/reception without
HDLC framing is performed i.e. without FLAG generation/recognition, CRC generation/
check, bitstuffing mechanism. This allows user specific protocol variations.
Note:
The extended Transparent Mode of the C165UTAH is implemented according to
the so called "LSB-First" methode. If the "MSB-First" methode is needed, e.g. for
voice traffic application, a look-up table using software could be applied.
fully transparent
16.7.2
Data Reception
16.7.2.1
General Description
The 8-byte RFIFO is controlled by the CPU, which will act as master. The control of the
data transfer between the CPU and the HDLC controller is handled via interrupts (HDLC
controller
→
CPU) and commands (CPU
→
HDLC controller).
There are four different interrupt indications in the ISTAH register concerned with the
reception of data:
–
RPF
(
R
eceive
P
ool
F
ull) interrupt, indicating that a data word/byte can be read from
RFIFO.
–
RME
(
R
eceive
M
essage
E
nd) interrupt, indicating that the reception of one message
is completed.
–
RFO
(
R
eceive
F
rame
O
verflow) interrupt, indicating that a complete frame could not
be stored in RFIFO and is therefore lost as the RFIFO is occupied. This occurs if the
CPU fails to respond quickly enough to RPF/RME interrupts since previous data was
not read by the CPU.
–
FFO
(
F
ollowing
F
rame
O
verflow) interrupt, indicating that a new frame could not be
stored in the RFIFO and therefore lost as the RFIFO is occupied. This occurs if either
there is still data in the RFIFO of the previous frame or the CPU has not acknowledged
the RME interrupt. Acknowledgment is done by writing ’1’ to the RME bit.
There is one control command that is used with the reception of data: