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C165UTAH
IOM-2 Interface Controller
Data Sheet
380
2001-02-23
asserted as soon as there is space for one data block in the TFIFO. Transmission in this
conjunction means the HDLC controller has send all data to the IOM-2 unit. The actual
transmission of the bits on the IOM-2 line can have some BCL cycles delay.
16.7.3.2
Possible Error Conditions during Transmission of Frames
If the transmitter sees an empty FIFO, i.e. if the microcontroller does not react quickly
enough to an XPR interrupt, an XDU (transmit data underrun) interrupt will be raised. If
the HDLC channel becomes unavailable during transmission the transmitter tries to
repeat the current frame as specified in the LAPD protocol. This is impossible after the
first data block has been sent (8 bytes), in this case an XMR transmit message repeat
interrupt is set and the microcontroller has to send the whole frame again.
Both XMR and XDU interrupts cause a reset of the TFIFO. The TFIFO is locked while an
XMR or XDU interrupt is pending, i.e. all write actions of the microcontroller will be
ignored as long as the microcontroller has not read the ISTAH register with the set XDU,
XMR interrupts.
If the microcontroller writes to a full FIFO, the data in the TFIFO will be corrupted and the
STAR.XDOV bit is set. If this happens, the microcontroller has to abort the transmission
by CMDR.XRES and to restart.
16.7.3.3
Transmit Frame Structure
The transmission of transparent frames (XTF command) is shown in
Figure 131
.
For transparent frames, the whole frame including address and control field must be
written to the TFIFO. The host configures whether the CRC is generated and appended
to the frame (default) or not (selected in MODEH.XCRC).
Furthermore, the host selects the interframe time fill signal which is transmitted between
HDLC frames (MODEH:ITF). One option is to send continuous flags (’01111110’),
however if D-channel access handling is required, the signal must be set to idle
(continuous ’1’s are transmitted).