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C165UTAH
Central Processor Unit
Data Sheet
55
2001-02-23
5
Central Processor Unit
Basic tasks of the CPU are to fetch and decode instructions, to supply operands for the
arithmetic and logic unit (ALU), to perform operations on these operands in the ALU, and
to store the previously calculated results. As the CPU is the main engine of the
C165UTAH controller, it is also affected by certain actions of the peripheral subsystem.
Since a four stage pipeline is implemented in the C165UTAH, up to four instructions can
be processed in parallel. Most instructions of the C165UTAH are executed in one
machine cycle (2 CPU clock cycles) due to this parallelism. This chapter describes how
the pipeline works for sequential and branch instructions in general, and which hardware
provisions have been made to speed the execution of jump instructions in particular. The
general instruction timing is described including standard and exceptional timing.
While internal memory accesses are normally performed by the CPU itself, external
peripheral or memory accesses are performed by a particular on-chip External Bus
Controller (EBC), which is automatically invoked by the CPU whenever a code or data
address refers to the external address space. If possible, the CPU continues operating
while an external memory access is in progress. If external data are required but are not
yet available, or if a new external memory access is requested by the CPU, before a
previous access has been completed, the CPU will be held by the EBC until the request
can be satisfied. The EBC is described in a dedicated chapter.
Figure 12
CPU Block Diagram
MCB02147
CPU
SP
STKOV
STKUN
Instr. Reg.
Instr. Ptr.
Exec. Unit
4-Stage
Pipeline
MDH
MDL
PSW
SYSCON
Context Ptr.
Mul/Div-HW
Bit-Mask Gen
R15
R0
General
Purpose
Registers
Barrel - Shifter
ALU
(16-bit)
Data Page Ptr.
Code Seg. Ptr.
Internal
RAM
R15
R0
ROM
16
16
32
BUSCON 0
BUSCON 1
BUSCON 2
BUSCON 3
BUSCON 4
ADDRSEL 4
ADDRSEL 3
ADDRSEL 2
ADDRSEL 1