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| 型號： | COP8CDR9KMT8 |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 49/111頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU EEPROM 8BIT 32K 56-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 34 |
| 系列： | COP8™ 8C |
| 核心處理器： | COP8 |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 連通性： | Microwire/Plus（SPI），UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 49 |
| 程序存儲器容量： | 32KB（32K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 16x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 56-TFSOP（0.240"，6.10mm 寬） |
| 包裝： | 管件 |
| 其它名稱： | *COP8CDR9KMT8 |
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SNOS535I – OCTOBER 2000 – REVISED MARCH 2013
Table 5-12. Typical Flash Memory Endurance
Low End of Operating Temp Range
Erase Time
40°C
20°C
0°C
25°C
>25°C
1 ms
60k
100k
2 ms
60k
100k
3 ms
60k
100k
4 ms
60k
100k
5 ms
70k
100k
6 ms
80k
100k
7 ms
90k
100k
8 ms
100k
5.11 Timers
The device contains a very versatile set of timers (T0, T1, T2 and T3). Timers T1, T2 and T3 and
associated autoreload/capture registers power up containing random data.
5.11.1 TIMER T0 (IDLE TIMER)
The device supports applications that require maintaining real time and low power with the IDLE mode.
This IDLE mode support is furnished by the IDLE Timer T0, which is a 16-bit timer. The user cannot read
or write to the IDLE Timer T0, which is a count down timer.
As described in Power Saving Features, the clock to the IDLE Timer depends on which mode the device
is in. If the device is in High Speed mode, the clock to the IDLE Timer is the instruction cycle clock (one-
fifth of the CKI frequency). If the device is in Dual Clock mode or Low Speed mode, the clock to the IDLE
Timer is the 32 kHz clock. For the remainder of this section, the term “selected clock” will refer to the clock
selected by the Power Save mode of the device. During Dual Clock and Low Speed modes, the divide by
10 that creates the instruction cycle clock is disabled, to minimize power consumption.
In addition to its time base function, the Timer T0 supports the following functions:
Exit out of the Idle Mode (See Idle Mode description)
WATCHDOG logic (See WATCHDOG description)
Start up delay out of the HALT mode
Start up delay from BOR
Figure 5-9 is a functional block diagram showing the structure of the IDLE Timer and its associated
interrupt logic.
Bits 11 through 15 of the ITMR register can be selected for triggering the IDLE Timer interrupt. Each time
the selected bit underflows (every 4k, 8k, 16k, 32k or 64k selected clocks), the IDLE Timer interrupt
pending bit T0PND is set, thus generating an interrupt (if enabled), and bit 6 of the Port G data register is
reset, thus causing an exit from the IDLE mode if the device is in that mode.
In order for an interrupt to be generated, the IDLE Timer interrupt enable bit T0EN must be set, and the
GIE (Global Interrupt Enable) bit must also be set. The T0PND flag and T0EN bit are bits 5 and 4 of the
ICNTRL register, respectively. The interrupt can be used for any purpose. Typically, it is used to perform a
task upon exit from the IDLE mode. For more information on the IDLE mode, refer to Power Saving
The Idle Timer period is selected by bits 0–2 of the ITMR register Bit 3 of the ITMR Register is reserved
and should not be used as a software flag. Bits 4 through 7 of the ITMR Register are used by the dual
clock and are described in Power Saving Features.
42
Functional Description
Copyright 2000–2013, Texas Instruments Incorporated
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