參數(shù)資料
型號(hào)： COP8CDR9KMT8
廠商： National Semiconductor
文件頁(yè)數(shù)： 82/111頁(yè)
文件大?。?/td> 0K
描述： IC MCU EEPROM 8BIT 32K 56-TSSOP
標(biāo)準(zhǔn)包裝： 34
系列： COP8™ 8C
核心處理器： COP8
芯體尺寸： 8-位
速度： 20MHz
連通性： Microwire/Plus（SPI），UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 49
程序存儲(chǔ)器容量： 32KB（32K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 56-TFSOP（0.240"，6.10mm 寬）
包裝： 管件
其它名稱： *COP8CDR9KMT8
SNOS535I – OCTOBER 2000 – REVISED MARCH 2013
5.14.1.1.5 Busy Bit
The ADBSY bit of the ENAD register is used to control starting and stopping of the A/D conversion. When
ADBSY is cleared, the prescale logic is disabled and the A/D clock is turned off, drawing minimal power.
Setting the ADBSY bit starts the A/D clock and initiates a conversion based on the values currently in the
ENAD register. Normal completion of an A/D conversion clears the ADBSY bit and turns off the A/D
Converter.
If the user wishes to restart a conversion which is already in progress, this can be accomplished only by
writing a zero to the ADBSY bit to stop the current conversion and then by writing a one to ADBSY to start
a new conversion. This can be done in two consecutive instructions.
5.14.1.2 A/D Result Registers
There are two result registers for the A/D converter: the high 8 bits of the result and the low 2-bits of the
result. The format of these registers is shown in Figure 5-21, Figure 5-22. Both registers are read/write
registers, but in normal operation, the hardware writes the value into the register when the conversion is
complete and the software reads the value. Both registers are undefined upon Reset. They hold the
previous value until a new conversion overwrites them. When reading ADRSTL, bits 5-0 will read as 0.
Table 5-23. ADRSTH
Bit 7
Bit 0
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Table 5-24. ADRSTL
Bit 7
Bit 0
Bit 1
Bit 0
0
5.14.2 A/D OPERATION
The A/D conversion is completed within fifteen A/D converter clocks. The A/D Converter interface works
as follows. Setting the ADBSY bit in the A/D control register ENAD initiates an A/D conversion. The
conversion sequence starts at the beginning of the write to ENAD operation which sets ADBSY, thus
powering up the A/D. At the first edge of the Converter clock following the write operation, the sample
signal turns on for three clock cycles. At the end of the conversion, the internal conversion complete signal
will clear the ADBSY bit and power down the A/D. The A/D 10-bit result is immediately loaded into the A/D
result registers (ADRSTH and ADRSTL) upon completion.
Inadvertent changes to the ENAD register during conversion are prevented by the control logic of the A/D.
Any attempt to write any bit of the ENAD Register except ADBSY, while ADBSY is a one, is ignored.
ADBSY must be cleared either by completion of an A/D conversion or by the user before the prescaler,
conversion mode or channel select values can be changed. After stopping the current conversion, the
user can load different values for the prescaler, conversion mode or channel select and start a new
conversion in one instruction.
5.14.2.1 Prescaler
The A/D Converter (A/D) contains a prescaler option that allows two different clock speed selections as
shown in Table 5-22. The A/D clock frequency is equal to MCLK divided by the prescaler value. Note that
the prescaler value must be chosen such that the A/D clock falls within the specified range. The maximum
A/D frequency is 1.25 MHz. This equates to a 800 ns A/D clock cycle.
72
Functional Description
Copyright 2000–2013, Texas Instruments Incorporated
Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9
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