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| 型號(hào)： | COP8CDR9KMT8 |
| 廠商： | National Semiconductor |
| 文件頁(yè)數(shù)： | 56/111頁(yè) |
| 文件大小： | 0K |
| 描述： | IC MCU EEPROM 8BIT 32K 56-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 34 |
| 系列： | COP8™ 8C |
| 核心處理器： | COP8 |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 連通性： | Microwire/Plus（SPI），UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 49 |
| 程序存儲(chǔ)器容量： | 32KB（32K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 16x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 56-TFSOP（0.240"，6.10mm 寬） |
| 包裝： | 管件 |
| 其它名稱： | *COP8CDR9KMT8 |
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SNOS535I – OCTOBER 2000 – REVISED MARCH 2013
Figure 5-13. Diagram of Power Save Modes
5.12.1 POWER SAVE MODE CONTROL REGISTER
The ITMR control register allows for navigation between the three different modes of operation. It is also
used for the Idle Timer. The register bit assignments are shown below. This register is cleared to 40 (hex)
by Reset as shown below.
LSON
HSON
DCEN
CCK
RSVD
ITSEL2
ITSEL1
ITSEL0
SEL
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LSON:
This bit is used to turn-on the low-speed oscillator. When LSON = 0, the low speed oscillator
is off. When LSON = 1, the low speed oscillator is on. There is a startup time associated with
this oscillator. See the Control Registers section.
HSON:
This bit is used to turn-on the high speed oscillator. When HSON = 0, the high speed
oscillator is off. When HSON = 1, the high speed oscillator is on. There is a startup time
associated with this oscillator. See the startup time table in the Control Registers section.
DCEN:
This bit selects the clock source for the Idle Timer. If this bit = 0, then the high speed clock is
the clock source for the Idle Timer. If this bit = 1, then the low speed clock is the clock
source for the Idle Timer. The low speed oscillator must be started and stabilized before
setting this bit to a 1.
CCKSEL:
This bit selects whether the high speed clock or low speed clock is gated to the
microcontroller core. When this bit = 0, the Core clock will be the high speed clock. When
this bit = 1, then the Core clock will be the low speed clock. Before switching this bit to either
state, the appropriate clock should be turned on and stabilized.
DCEN
CCKSEL
0
High Speed Mode. Core and Idle Timer Clock = High Speed
1
0
Dual Clock Mode. Core clock = High Speed; Idle Timer = Low Speed
1
Low Speed Mode. Core and Idle Timer Clock = Low Speed
0
1
Invalid. If this is detected, the Low Speed Mode will be forced.
RSVD:
This bit is reserved and must be 0.
Bits 2–0:
These are bits used to control the Idle Timer. See TIMER T0 (IDLE TIMER) for the
Copyright 2000–2013, Texas Instruments Incorporated
Functional Description
49
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