參數(shù)資料
型號(hào)： COP8CDR9KMT8
廠商： National Semiconductor
文件頁(yè)數(shù)： 93/111頁(yè)
文件大小： 0K
描述： IC MCU EEPROM 8BIT 32K 56-TSSOP
標(biāo)準(zhǔn)包裝： 34
系列： COP8™ 8C
核心處理器： COP8
芯體尺寸： 8-位
速度： 20MHz
連通性： Microwire/Plus（SPI），UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 49
程序存儲(chǔ)器容量： 32KB（32K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 56-TFSOP（0.240"，6.10mm 寬）
包裝： 管件
其它名稱： *COP8CDR9KMT8
SNOS535I – OCTOBER 2000 – REVISED MARCH 2013
Table 5-27. WATCHDOG Service Window Select (continued)
Clock
Service Window
WDSVR
Monitor
for High Speed Mode
for Dual Clock & Low Speed Modes
Bit 7
Bit 6
Bit 0
(Lower-Upper Limits)
X
1
Clock Monitor Enabled
5.16.1 CLOCK MONITOR
The Clock Monitor aboard the device can be selected or deselected under program control. The Clock
Monitor is ensured not to reject the clock if the instruction cycle clock (1/tC) is greater or equal to 5 kHz.
This equates to a clock input rate on the selected oscillator of greater or equal to 25 kHz.
5.16.2 WATCHDOG/CLOCK MONITOR OPERATION
The WATCHDOG is enabled by bit 2 of the Option register. When this Option bit is 0, the WATCHDOG is
enabled and pin G1 becomes the WATCHDOG output with a weak pull-up.
The WATCHDOG and Clock Monitor are disabled during reset. The device comes out of reset with the
WATCHDOG armed, the WATCHDOG Window Select bits (bits 6, 7 of the WDSVR Register) set, and the
Clock Monitor bit (bit 0 of the WDSVR Register) enabled. Thus, a Clock Monitor error will occur after
coming out of reset, if the instruction cycle clock frequency has not reached a minimum specified value,
including the case where the oscillator fails to start.
The WDSVR register can be written to only once after reset and the key data (bits 5 through 1 of the
WDSVR Register) must match to be a valid write. This write to the WDSVR register involves two
irrevocable choices: (i) the selection of the WATCHDOG service window (ii) enabling or disabling of the
Clock Monitor. Hence, the first write to WDSVR Register involves selecting or deselecting the Clock
Monitor, select the WATCHDOG service window and match the WATCHDOG key data. Subsequent
writes to the WDSVR register will compare the value being written by the user to the WATCHDOG service
window value, the key data and the Clock Monitor Enable (all bits) in the WDSVR Register. Table 5-28
shows the sequence of events that can occur.
The user must service the WATCHDOG at least once before the upper limit of the service window expires.
The WATCHDOG may not be serviced more than once in every lower limit of the service window.
When jumping to the boot ROM for ISP and virtual E2 operations, the hardware will disable the lower
window error and perform an immediate WATCHDOG service. The ISP routines will service the
WATCHDOG within the selected upper window. The ISP routines will service the WATCHDOG
immediately prior to returning execution back to the user's code in flash. Therefore, after returning to flash
memory, the user can service the WATCHDOG anytime following the return from boot ROM, but must
service it within the selected upper window to avoid a WATCHDOG error.
The WATCHDOG has an output pin associated with it. This is the WDOUT pin, on pin 1 of the port G.
WDOUT is active low. The WDOUT pin has a weak pull-up in the inactive state. Upon triggering the
WATCHDOG, the logic will pull the WDOUT (G1) pin low for an additional 16–32 cycles after the signal
level on WDOUT pin goes below the lower Schmitt trigger threshold. After this delay, the device will stop
forcing the WDOUT output low. The WATCHDOG service window will restart when the WDOUT pin goes
high.
A WATCHDOG service while the WDOUT signal is active will be ignored. The state of the WDOUT pin is
not ensured on reset, but if it powers up low then the WATCHDOG will time out and WDOUT will go high.
The Clock Monitor forces the G1 pin low upon detecting a clock frequency error. The Clock Monitor error
will continue until the clock frequency has reached the minimum specified value, after which the G1 output
will go high following 16–32 clock cycles. The Clock Monitor generates a continual Clock Monitor error if
the oscillator fails to start, or fails to reach the minimum specified frequency. The specification for the
Clock Monitor is as follows:
1/tC > 5 kHz—No clock rejection.
82
Functional Description
Copyright 2000–2013, Texas Instruments Incorporated
Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9
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