參數(shù)資料
型號: COP8CDR9KMT8
廠商: National Semiconductor
文件頁數(shù): 50/111頁
文件大小: 0K
描述: IC MCU EEPROM 8BIT 32K 56-TSSOP
標準包裝: 34
系列: COP8™ 8C
核心處理器: COP8
芯體尺寸: 8-位
速度: 20MHz
連通性: Microwire/Plus(SPI),UART/USART
外圍設備: POR,PWM,WDT
輸入/輸出數(shù): 49
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉換器: A/D 16x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 56-TFSOP(0.240",6.10mm 寬)
包裝: 管件
其它名稱: *COP8CDR9KMT8
SNOS535I – OCTOBER 2000 – REVISED MARCH 2013
Figure 5-9. Functional Block Diagram for Idle Timer T0
Table 5-13. Idle Timer Window Length
Idle Timer Period
ITSEL2
ITSEL1
ITSEL0
High Speed
Dual Clock or
Mode
Low Speed Mode
0
4,096 inst. cycles
0.125 seconds
0
1
8,192 inst. cycles
0.25 seconds
0
1
0
16,384 inst. cycles
0.5 seconds
0
1
32,768 inst. cycles
1 second
1
0
65,536 inst. cycles
2 seconds
1
0
1
Reserved - Undefined
1
0
Reserved - Undefined
1
Reserved - Undefined
The ITSEL bits of the ITMR register are cleared on Reset and the Idle Timer period is reset to 4,096
instruction cycles.
5.11.1.1 ITMR Register
CCK
LSON
HSON
DCEN
RSVD
ITSEL2
ITSEL1
ITSEL0
SEL
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bits 7–4:
NOTE
Documentation for previous COP8 devices, which included the Programmable Idle Timer,
recommended the user write zero to the high order bits of the ITMR Register. If existing
programs are updated to use this device, writing zero to these bits will cause the device to
RSVD: This bit is reserved and must be set to 0.
ITSEL2:0: Selects the Idle Timer period as described in Table 5-13, Idle Timer Window Length.
Copyright 2000–2013, Texas Instruments Incorporated
Functional Description
43
Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9
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