參數(shù)資料
型號： COP8CDR9KMT8
廠商： National Semiconductor
文件頁數(shù)： 95/111頁
文件大?。?/td> 0K
描述： IC MCU EEPROM 8BIT 32K 56-TSSOP
標(biāo)準(zhǔn)包裝： 34
系列： COP8™ 8C
核心處理器： COP8
芯體尺寸： 8-位
速度： 20MHz
連通性： Microwire/Plus（SPI），UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 49
程序存儲器容量： 32KB（32K x 8）
程序存儲器類型： 閃存
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 56-TFSOP（0.240"，6.10mm 寬）
包裝： 管件
其它名稱： *COP8CDR9KMT8
SNOS535I – OCTOBER 2000 – REVISED MARCH 2013
5.16.4 DETECTION OF ILLEGAL CONDITIONS
The device can detect various illegal conditions resulting from coding errors, transient noise, power supply
voltage drops, runaway programs, etc.
Reading of unprogrammed ROM gets zeros. The opcode for software interrupt is 00. If the program
fetches instructions from unprogrammed ROM, this will force a software interrupt, thus signaling that an
illegal condition has occurred.
The subroutine stack grows down for each call (jump to subroutine), interrupt, or PUSH, and grows up for
each return or POP. The stack pointer is initialized to RAM location 06F Hex during reset. Consequently, if
there are more returns than calls, the stack pointer will point to addresses 070 and 071 Hex (which are
undefined RAM). Undefined RAM from addresses 070 to 07F (Segment 0), and all other segments (i.e.,
Segments 4... etc.) is read as all 1's, which in turn will cause the program to return to address 7FFF Hex.
The Option Register is located at this location and, when accessed by an instruction fetch, will respond
with an INTR instruction (all 0's) to generate a software interrupt, signalling an illegal condition on overpop
of the stack.
Thus, the chip can detect the following illegal conditions:
1. Executing from undefined Program Memory
2. Over “POP”ing the stack by having more returns than calls.
When the software interrupt occurs, the user can re-initialize the stack pointer and do a recovery
procedure before restarting (this recovery program is probably similar to that following reset, but might not
contain the same program initialization procedures). The recovery program should reset the software
interrupt pending bit using the RPND instruction.
5.17 MICROWIRE/PLUS
MICROWIRE/PLUS
is
a
serial
SPI
compatible
synchronous
communications
interface.
The
MICROWIRE/PLUS capability enables the device to interface with MICROWIRE/PLUS or SPI peripherals
(i.e. A/D converters, display drivers, EEPROMs etc.) and with other microcontrollers which support the
MICROWIRE/PLUS or SPI interface. It consists of an 8-bit serial shift register (SIO) with serial data input
(SI), serial data output (SO) and serial shift clock (SK). Figure 5-26 shows a block diagram of the
MICROWIRE/PLUS logic.
The shift clock can be selected from either an internal source or an external source. Operating the
MICROWIRE/PLUS arrangement with the internal clock source is called the Master mode of operation.
Similarly, operating the MICROWIRE/PLUS arrangement with an external shift clock is called the Slave
mode of operation.
The CNTRL register is used to configure and control the MICROWIRE/PLUS mode. To use the
MICROWIRE/PLUS, the MSEL bit in the CNTRL register is set to one. In the master mode, the SK clock
rate is selected by the two bits, SL0 and SL1, in the CNTRL register. Table 5-29 details the different clock
rates that may be selected.
Table 5-29. MICROWIRE/PLUS
Master Mode Clock Select
SL1
SL0
SK Period(1)
0
2 × tC
0
1
4 × tC
1
x
8 × tC
(1)
Where tC is the instruction cycle clock
84
Functional Description
Copyright 2000–2013, Texas Instruments Incorporated
Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9
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