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| 型號： | COP8CDR9KMT8 |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 80/111頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU EEPROM 8BIT 32K 56-TSSOP |
| 標準包裝： | 34 |
| 系列： | COP8™ 8C |
| 核心處理器： | COP8 |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 連通性： | Microwire/Plus（SPI），UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 49 |
| 程序存儲器容量： | 32KB（32K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 16x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 56-TFSOP（0.240"，6.10mm 寬） |
| 包裝： | 管件 |
| 其它名稱： | *COP8CDR9KMT8 |
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SNOS535I – OCTOBER 2000 – REVISED MARCH 2013
Table 5-20. A/D Converter Channel Selection when the Multiplexor Output is Enabled
Mode Select
ADMOD = 0
Mux Output
Select Bits
ADMOD = 1
Single Ended
Enabled
Differential Mode
Mode
ADCH3
ADCH2
ADCH1
ADCH0
Channel No.
Channel Pairs (+,
MUX
)
0
0, 1
1
0
1
1, 0
1
0
1
0
2
2, 3
1
0
1
3
3, 2
1
0
1
0
4
4, 5
1
0
1
0
1
5
5, 4
1
0
1
0
6
6, 7
1
0
1
7
7, 6
1
0
8
8, 9
1
0
1
9
9, 8
1
0
1
0
10
10, 11
1
0
1
11
11, 10
1
0
12
Not Used(1)
1
0
1
13
ADC13 is
1
Mux Output
See(1)
1
0
ADCH14 is
1
Mux Output(2)
Mux Output +
See (2)
1
ADCH15 is
1
A/D Input(2)
(1)
This Input Channel Selection should not be used in Differential Mode when the Multiplexor Output is enabled.
(2)
This Input Channel Selection should not be used when the Multiplexor Output is enabled.
5.14.1.1.2 Multiplexor Output Select
This 1-bit field allows the output of the A/D multiplexor and the input to the A/D to be connected directly to
external pins. This allows for an external, common filter/signal conditioning circuit to be applied to all
channels. The output of the external conditioning circuit can then be connected directly to the input of the
Sample and Hold input on the A/D Converter. See Figure 5-20 for the single ended mode diagram. The
Multiplexor output is connected to ADCH14 and the A/D input is connected to ADCH15. For Differential
mode, the differential multiplexor outputs are available and should be converted to a single ended voltage
for connection to the A/D Converter Input. See Figure 5-21.
The channel assignments for this mode are shown in Table 5-21.
When using the Mux Output feature, the delay though the internal multiplexor to the pin, plus the delay of
the external filter circuit, plus the internal delay to the Sample and Hold will exceed the three clock cycles
that's allowed in the conversion. This adds the requirement that, whenever the MUX bit = 1, that the
channel selected by ADCH3:0 bits be enabled, even when ADBSY = 0, and gated to the mux output pin.
The input path to the A/D converter is also enabled. This allows the input channel to be selected and
settled before starting a conversion. The sequence to perform conversions using the Mux Out feature is a
multistep process and is listed below.
1. Select the desired channel and operating modes and load them into ENAD without setting ADBSY.
2. Wait the appropriate time until the analog input has settled. This will depend on the application and the
response of the external circuit.
3. Select the same desired channel and operating modes used in step 1 and load them into ENAD and
also set ADBSY or set ADBSY by using the SBIT instruction. This will start the conversion.
70
Functional Description
Copyright 2000–2013, Texas Instruments Incorporated
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