參數(shù)資料
型號: CY3950V484-125BBC
廠商: Cypress Semiconductor Corp.
英文描述: CPLDs at FPGA Densities
中文描述: CPLD器件在FPGA的密度
文件頁數(shù): 74/86頁
文件大?。?/td> 1212K
代理商: CY3950V484-125BBC
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *H
Page 76 of 86
Y7
IO2
Y8
NC
IO2
Y9
NC
IO2
Y10
IO/VREF2
Y11
IO2
Y12
IO3
Y13
IO/VREF3
Y14
IO3
Y15
IO3
Y16
IO3
Y17
IO3
Y18
NC
IO3
Y19
NC
IO3
Y20
NC
IO3
Y21
NC
IO3
Y22
NC
IO3
AA1
GND
AA2
GND
AA3
NC
IO2
AA4
VCCIO2
AA5
IO/VREF2
AA6
IO2
AA7
NC
IO2
AA8
IO2
AA9
NC
VCCIO2
AA10
NC
IO2
AA11
IO2
AA12
IO3
AA13
IO3
AA14
NC
VCCIO3
AA15
IO3
AA16
NC
IO3
IO3[20]
IO3
AA17
NC
IO3
IO3[20]
IO3
AA18
IO/VREF3
AA19
VCCIO3
AA20
NC
IO3
AA21
GND
AA22
GND
AB1
GND
AB2
GND
AB3
NC
IO/VREF2
AB4
NC
IO/VREF2
Note:
20. These I/Os have a slightly higher tPD (propagation delay) than the rest of the pins. The use of these pins on the same packages of different densities or the
pins in the same relative position in smaller or larger FBGAs for signals with critical timing should be avoided. When first implementing a design in these
packages, the timing-driven routing of Warp 6.2 and later versions will ensure these pins are avoided when routing critical signal.
Table 14. 484 FBGA Pin Table (continued)
Pin
CY39050
CY39100
CY39165
CY39200
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CY3950V484-125MBI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities