參數(shù)資料
型號： CY3950V484-125BBC
廠商： Cypress Semiconductor Corp.
英文描述： CPLDs at FPGA Densities
中文描述： CPLD器件在FPGA的密度
文件頁數(shù)： 9/86頁
文件大?。?/td> 1212K
代理商： CY3950V484-125BBC
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *H
Page 17 of 86
Power-up Sequence Requirements
Upon power-up, all the outputs remain three-stated until all
the VCC pins have powered-up to the nominal voltage and
the part has completed configuration.
The part will not start configuration until VCC, VCCIO,
VCCJTAG, VCCCNFG, VCCPLL and VCCPRG have reached
nominal voltage.
VCC pins can be powered up in any order. This includes
VCC, VCCIO, VCCJTAG, VCCCNFG, VCCPLL and VCCPRG.
All VCCIOs on a bank should be tied to the same potential
and powered up together.
All VCCIOs (even the unused banks) need to be powered up
to at least 1.5V before configuration has completed.
Maximum ramp time for all VCCs should be 0V to nominal
voltage in 100 ms.
Notes:
9.
PCI spec (rev 2.2) requires the IDSEL pin to have capacitance less than or equal to 8 pF. Delta39K Pin Tables starting from page 45, identify all the I/O pins in
a given package, which can be used as IDSEL in a PCI design. All other I/O pins meet the PCI requirement of capacitance less than or equal to 10 pf.
10. The number of I/Os which can be used in each I/O bank depends on the type of I/O standards and the number of VCCIO and GND pins being used. Please refer
to the application note titled “Delta39K and Quantum38K I/O Standards and Configurations” for details.
The source current limit per I/O bank per Vccio pin is 165 mA.
The sink current limit per I/O bank per GND pin is 230 mA.
11. See “Power-up Sequence Requirements” below for VCCIO requirement.
12. 25W resistor terminated to termination voltage of 1.5V.
Capacitance
Parameter
Description
Test Conditions
Min.
Max.
Unit
CI/O
Input/Output Capacitance
Vin = VCCIO @ f = 1 MHz 25°C
10
pF
CCLK
Clock Signal Capacitance
Vin = VCCIO @ f = 1 MHz 25°C
5
12
pF
CPCI
PCI-compliant[9] Capacitance
Vin = VCCIO @ f = 1 MHz 25°C
8
pF
DC Characteristics (I/O)[10]
I/O Standards
VREF
(V)
VCCIO
(V)
VOH (V)
VOL (V)
VIH (V)
VIL (V)
@ IOH =VOH (min.)
@ IOL =
VOL
(max.)
Min.
Max.
Min.
Max.
LVTTL –2 mA
N/A
3.3
–2 mA
2.4
2 mA
0.4
2.0V
VCCIO + 0.3 –0.3V
0.8V
LVTTL –4 mA
3.3
–4 mA
2.4
4 mA
0.4
2.0V
VCCIO + 0.3 –0.3V
0.8V
LVTTL –6 mA
3.3
–6 mA
2.4
6 mA
0.4
2.0V
VCCIO + 0.3 –0.3V
0.8V
LVTTL –8 mA
3.3
–8 mA
2.4
8 mA
0.4
2.0V
VCCIO + 0.3 –0.3V
0.8V
LVTTL –12 mA
3.3
–12 mA
2.4
12 mA
0.4
2.0V
VCCIO + 0.3 –0.3V
0.8V
LVTTL –16 mA
3.3
–16 mA
2.4
16 mA
0.4
2.0V
VCCIO + 0.3 –0.3V
0.8V
LVTTL –24 mA
3.3
–24 mA
2.4
24 mA
0.4
2.0V
VCCIO + 0.3 –0.3V
0.8V
LVCMOS
3.3
–0.1 mA
VCCIO – 0.2V
0.1 mA
0.2
2.0V
VCCIO + 0.3 –0.3V
0.8V
LVCMOS3
3.0
–0.1 mA
VCCIO – 0.2V
0.1 mA
0.2
2.0V
VCCIO + 0.3 –0.3V
0.8V
LVCMOS2
2.5
–0.1 mA
2.1
0.1 mA
0.2
1.7V
VCCIO + 0.3 –0.3V
0.7V
–1.0 mA
2.0
1.0 mA
0.4
–2.0 mA
1.7
2.0 mA
0.7
LVCMOS18
1.8
–2 mA
VCCIO – 0.45V 2.0 mA
0.45
0.65VCCIO VCCIO + 0.3 –0.3V 0.35VCCIO
3.3V PCI
3.3
–0.5 mA
0.9VCCIO
1.5 mA
0.1VCCIO
0.5VCCIO
VCCIO + 0.5 –0.5V
0.3VCCIO
GTL+
1.0
[11]
36 mA[12]
0.6
VREF + 0.2
VREF – 0.2
SSTL3 I
1.5
3.3
–8 mA
VCCIO – 1.1V
8 mA
0.7
VREF + 0.2 VCCIO + 0.3 –0.3V VREF – 0.2
SSTL3 II
1.5
3.3
–16 mA
VCCIO – 0.9V
16 mA
0.5
VREF + 0.2 VCCIO + 0.3 –0.3V VREF – 0.2
SSTL2 I
1.25
2.5
–7.6 mA VCCIO – 0.62V 7.6 mA
0.54
VREF + 0.18 VCCIO + 0.3 –0.3V VREF – 0.18
SSTL2 II
1.25
2.5
–15.2 mA VCCIO – 0.43V 15.2 mA
0.35
VREF + 0.18 VCCIO + 0.3 –0.3V VREF – 0.18
HSTL I
0.75
1.5
–8 mA
VCCIO – 0.4V
8 mA
0.4
VREF + 0.1 VCCIO + 0.3 –0.3V VREF – 0.1
HSTL II
0.75
1.5
–16 mA
VCCIO – 0.4V
16 mA
0.4
VREF + 0.1 VCCIO + 0.3 –0.3V VREF – 0.1
HSTL III
0.9
1.5
–8 mA
VCCIO – 0.4V
24 mA
0.4
VREF + 0.1 VCCIO + 0.3 –0.3V VREF – 0.1
HSTL IV
0.9
1.5
–8 mA
VCCIO – 0.4V
48 mA
0.4
VREF + 0.1 VCCIO + 0.3 –0.3V VREF – 0.1
Configuration Parameters
Parameter
Description
Min.
Unit
tRECONFIG
Reconfig pin LOW time before it goes HIGH
200
ns
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相關代理商/技術參數(shù)
參數(shù)描述
CY3950V484-125BBI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY3950V484-125BGC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
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CY3950V484-125MBC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY3950V484-125MBI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
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