參數(shù)資料
型號(hào)： CY7C1515AV18-250BZXI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： SRAM
英文描述： 2M X 36 QDR SRAM, 0.45 ns, PBGA165
封裝： 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165
文件頁(yè)數(shù)： 1/31頁(yè)
文件大?。?/td> 774K
代理商： CY7C1515AV18-250BZXI
72-Mbit QDR-II SRAM 4-Word
Burst Architecture
CY7C1511AV18, CY7C1526AV18
CY7C1513AV18, CY7C1515AV18
Cypress Semiconductor Corporation
198 Champion Court
San Jose
, CA 95134-1709
408-943-2600
Document Number: 001-06985 Rev. *D
Revised June 14, 2008
Features
■ Separate independent read and write data ports
Supports concurrent transactions
■ 300 MHz clock for high bandwidth
■ 4-word burst for reducing address bus frequency
■ Double Data Rate (DDR) interfaces on both read and write ports
(data transferred at 600 MHz) at 300 MHz
■ Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
■ Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
■ Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
■ Single multiplexed address input bus latches address inputs
for read and write ports
■ Separate port selects for depth expansion
■ Synchronous internally self-timed writes
■ QDR-II operates with 1.5 cycle read latency when the Delay
Lock Loop (DLL) is enabled
■ Operates as a QDR-I device with 1 cycle read latency in DLL
off mode
■ Available in x 8, x 9, x 18, and x 36 configurations
■ Full data coherency, providing most current data
■ Core VDD = 1.8 (± 0.1V); IO VDDQ = 1.4V to VDD
■ Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ Variable drive HSTL output buffers
■ JTAG 1149.1 compatible test access port
■ Delay Lock Loop (DLL) for accurate data placement
Configurations
CY7C1511AV18 – 8M x 8
CY7C1526AV18 – 8M x 9
CY7C1513AV18 – 4M x 18
CY7C1515AV18 – 2M x 36
Functional Description
The CY7C1511AV18, CY7C1526AV18, CY7C1513AV18, and
CY7C1515AV18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR-II architecture. QDR-II architecture
consists of two separate ports: the read port and the write port to
access the memory array. The read port has dedicated data
outputs to support read operations and the write port has
dedicated data inputs to support write operations. QDR-II archi-
tecture has separate data inputs and data outputs to completely
eliminate the need to “turn-around” the data bus that exists with
common IO devices. Each port can be accessed through a
common address bus. Addresses for read and write addresses
are latched on alternate rising edges of the input (K) clock.
Accesses to the QDR-II read and write ports are completely
independent of one another. To maximize data throughput, both
read and write ports are equipped with DDR interfaces. Each
address
location
is
associated
with
four
8-bit
words
(CY7C1511AV18), 9-bit words (CY7C1526AV18), 18-bit words
(CY7C1513AV18), or 36-bit words (CY7C1515AV18) that burst
sequentially into or out of the device. Because data can be trans-
ferred into and out of the device on every rising edge of both input
clocks (K and K and C and C), memory bandwidth is maximized
while
simplifying
system
design
by
eliminating
bus
“turn-arounds”.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Selection Guide
Description
300 MHz
278 MHz
250 MHz
200 MHz
167 MHz
Unit
Maximum Operating Frequency
300
278
250
200
167
MHz
Maximum Operating Current
x8
930
865
790
655
570
mA
x9
940
870
795
660
575
x18
1020
950
865
715
615
x36
1230
1140
1040
850
725
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C1515JV18-167BZI 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 2Mx36 1.8V QDR Burst 4 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1515JV18-300BZC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 2M x 36 1.8V QDR 靜態(tài)隨機(jī)存取存儲(chǔ)器 Four-Word Burst RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1515JV18-300BZI 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 2Mx36 1.8V QDR Burst 4 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1515JV18-300BZXC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 2M x 36 1.8V QDR 靜態(tài)隨機(jī)存取存儲(chǔ)器 Four-Word Burst RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1515JV18-333BZXC 制造商:Cypress Semiconductor 功能描述:IC SRAM 72MBIT 333MHZ 165-FPBGA - Trays
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