- 您現(xiàn)在的位置：買賣IC網 > PDF目錄298975 > CY7C1347D-250BGC (CYPRESS SEMICONDUCTOR CORP) 128K X 36 CACHE SRAM, 2.4 ns, PBGA119 PDF資料下載
參數(shù)資料
| 型號： | CY7C1347D-250BGC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 128K X 36 CACHE SRAM, 2.4 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119 |
| 文件頁數(shù)： | 16/21頁 |
| 文件大?。?/td> | 2790K |
| 代理商： | CY7C1347D-250BGC |
CY7C1347D
Document #: 38-05022 Rev. *E
Page 4 of 21
CY7C1347D Pin Descriptions
BGA Pins
QFP Pins
Name
Type
Description
4P
4N
2A, 3A, 5A, 6A,
3B, 5B, 2C, 3C,
5C, 6C, 2R, 6R,
3T, 4T, 5T
37
36
35, 34, 33, 32,
100, 99, 82, 81,
44, 45, 46, 47,
48, 49, 50
A0
A1
A
Input-
Synchronous
Addresses: These inputs are registered and must meet the
set-up and hold times around the rising edge of CLK. The burst
counter generates internal addresses associated with A0 and
A1, during burst cycle and wait cycle.
5L
5G
3G
3L
93
94
95
96
BWa
BWb
BWc
BWd
Input-
Synchronous
Byte Write: A byte write is LOW for a Write cycle and HIGH for
a Read cycle. BWa controls DQa. BWb controls DQb. BWc
controls DQc. BWd controls DQd. Data I/O are high impedance
if either of these inputs are LOW, conditioned by BWE being
LOW.
4M
87
BWE
Input-
Synchronous
Write Enable: This active LOW input gates byte write operations
and must meet the set-up and hold times around the rising edge
of CLK.
4H
88
GW
Input-
Synchronous
Global Write: This active LOW input allows a full 36-bit Write to
occur independent of the BWE and BWn lines and must meet
the set-up and hold times around the rising edge of CLK.
4K
89
CLK
Input-
Synchronous
Clock: This signal registers the addresses, data, chip enables,
write control and burst control inputs on its rising edge. All
synchronous inputs must meet set-up and hold times around
the clock’s rising edge.
4E
98
CE
Input-
Synchronous
Chip Enable: This active LOW input is used to enable the device
and to gate ADSP.
6B
92
CE2
Input-
Synchronous
Chip Enable: This active LOW input is used to enable the
device.
2U
38
TMS
Input
IEEE 1149.1 test inputs. LVTTL-level inputs. If JTAG feature is
not utilized, this pin can be disconnected or connected to Vcc.
Pin Configurations (continued)
119-Ball BGA
Top View
12
34
56
7
A
VCCQ
A
ADSP
AA
VCCQ
B
NC
CE2
A
ADSC
ACE2
NC
C
NC
A
VCC
AA
NC
D
DQc
VSS
NC
VSS
DQb
E
DQc
VSS
CE
VSS
DQb
F
VCCQ
DQc
VSS
OE
VSS
DQb
VCCQ
G
DQc
BWc
ADV
BWb
DQb
H
DQc
VSS
GW
VSS
DQb
J
VCCQ
VCC
NC
VCC
NC
VCC
VCCQ
K
DQd
VSS
CLK
VSS
DQa
L
DQd
BWd
NC
BWa
DQa
M
VCCQ
DQd
VSS
BWE
VSS
DQa
VCCQ
N
DQd
VSS
A1
VSS
DQa
P
DQd
VSS
A0
VSS
DQa
R
NC
A
MODE
VCC
NC
A
NC
T
NC
A
NC
ZZ
U
VCCQ
TMS
TDI
TCK
TDO
NC
VCCQ
相關PDF資料 |
PDF描述 |
|---|---|
| CY7C1512JV18-267BZXC | 4M X 18 QDR SRAM, 0.45 ns, PBGA165 |
| CY7C1515AV18-250BZXI | 2M X 36 QDR SRAM, 0.45 ns, PBGA165 |
| CY7C1522JV18-250BZI | 8M X 8 DDR SRAM, 0.45 ns, PBGA165 |
| CY7C1524KV18-333BZI | 2M X 36 DDR SRAM, 0.45 ns, PBGA165 |
| CY7C1612KV18-333BZXC | 8M X 18 QDR SRAM, PBGA165 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1347DP | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1347F-100AC | 功能描述:IC SRAM 4.5MBIT 100MHZ 100LQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:96 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應商設備封裝:48-TSOP 包裝:托盤 |
| CY7C1347F-133AC | 功能描述:IC SRAM 4.5MBIT 133MHZ 100LQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:96 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應商設備封裝:48-TSOP 包裝:托盤 |
| CY7C1347F-133BGI | 制造商:Rochester Electronics LLC 功能描述:4M- 128KX36 3.3V PIPELINE 1CD STD. SPEED-SYNCHRONOUS SRAM - Bulk |
| CY7C1347F-166BGCT | 制造商:Cypress Semiconductor 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。