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參數(shù)資料
| 型號： | CY7C1347D-250BGC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 128K X 36 CACHE SRAM, 2.4 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119 |
| 文件頁數(shù)： | 17/21頁 |
| 文件大?。?/td> | 2790K |
| 代理商： | CY7C1347D-250BGC |
CY7C1347D
Document #: 38-05022 Rev. *E
Page 5 of 21
2U
39
TDI
Input
IEEE 1149.1 test inputs. LVTTL-level inputs. If JTAG feature is
not utilized, this pin can be disconnected or connected to VCC.
3U
43
TCK
Input
IEEE 1149.1 test inputs. LVTTL-level inputs. If JTAG feature is
not utilized, this pin can be disconnected or connected to VSS
or VCC.
5U
42
TDO
Output
IEEE 1149.1 test output. LVTTL-level output. If JTAG feature is
not utilized, this pin should be disconnected.
1B, 7B, 1C, 7C, 4D,
3J, 5J, 4L, 1R, 5R,
7R, 1T, 2T, 6T, 6U
14, 16, 66
NC
–
No Connect: These signals are not internally connected.
CY7C1347D Pin Descriptions (continued)
BGA Pins
QFP Pins
Name
Type
Description
Burst Address Table (MODE = NC/VCC)
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
A...A00
A...A01
A...A10
A...A11
A...A01
A...A00
A...A11
A...A10
A...A11
A...A00
A...A01
A...A11
A...A10
A...A01
A...A00
Burst Address Table (MODE = GND)
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
A...A00
A...A01
A...A10
A...A11
A...A01
A...A10
A...A11
A...A00
A...A10
A...A11
A...A00
A...A01
A...A11
A...A00
A...A01
A...A10
Truth Table [2, 3, 4, 5, 6, 7]
Operation
Address
Used
CE CE2 CE2 ADSP
ADSC
ADV
Write
OE
CLK
DQ
Deselected Cycle, Power-down
None
H
X
L
X
L-H
High-Z
Deselected Cycle, Power-down
None
L
X
L
X
L-H
High-Z
Deselected Cycle, Power-down
None
L
H
X
L
X
L-H
High-Z
Deselected Cycle, Power-down
None
L
X
L
H
L
X
L-H
High-Z
Deselected Cycle, Power-down
None
L
H
X
H
L
X
L-H
High-Z
Read Cycle, Begin Burst
External
L
H
L
X
L
L-H
Q
Read Cycle, Begin Burst
External
L
H
L
X
H
L-H
High-Z
Write Cycle, Begin Burst
External
L
H
L
X
L
X
L-H
D
Read Cycle, Begin Burst
External
L
H
L
X
H
L
L-H
Q
Read Cycle, Begin Burst
External
L
H
L
X
H
L-H
High-Z
Read Cycle, Continue Burst
Next
X
H
L
H
L
L-H
Q
Read Cycle, Continue Burst
Next
X
H
L
H
L-H
High-Z
Read Cycle, Continue Burst
Next
H
X
H
L
H
L
L-H
Q
Read Cycle, Continue Burst
Next
H
X
H
L
H
L-H
High-Z
Write Cycle, Continue Burst
Next
X
H
L
X
L-H
D
Write Cycle, Continue Burst
Next
H
X
H
L
X
L-H
D
Read Cycle, Suspend Burst
Current
X
H
L
L-H
Q
Read Cycle, Suspend Burst
Current
X
H
L-H
High-Z
Notes:
2. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
Write = L means [BWE + BWa*BWb*BWc*BWd]*GW equals LOW. Write = H means [BWE + BWa*BWb*BWc*BWd]*GW equals HIGH. BWa enables write to
DQa. BWb enables write to DQb. BWc enables write to DQc. BWd enables write to DQd.
3. All inputs except OE must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK.
4. Suspending burst generates wait cycle.
5. For a write operation following a read operation, OE must be HIGH before the input data required set-up time plus High-Z time for OE and staying HIGH throughout
the input data hold time.
6. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
7. ADSP LOW along with chip being selected always initiates a Read cycle at the L-H edge of CLK. A Write cycle can be performed by setting Write LOW for the
CLK L-H edge of the subsequent wait cycle. Refer to Write timing diagram for clarification.
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參數(shù)描述 |
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| CY7C1347DP | 制造商:Cypress Semiconductor 功能描述: |
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