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| 型號： | CY7C1347D-250BGC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 128K X 36 CACHE SRAM, 2.4 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119 |
| 文件頁數(shù)： | 18/21頁 |
| 文件大小： | 2790K |
| 代理商： | CY7C1347D-250BGC |
CY7C1347D
Document #: 38-05022 Rev. *E
Page 6 of 21
IEEE 1149.1 Serial Boundary Scan (JTAG)
Overview
This device incorporates a serial boundary scan access port
(TAP). This port is designed to operate in a manner consistent
with IEEE Standard 1149.1-1990 (commonly referred to as
JTAG), but does not implement all of the functions required for
IEEE 1149.1 compliance. Certain functions have been
modified or eliminated because their implementation places
extra delays in the critical speed path of the device. Never-
theless, the device supports the standard TAP controller archi-
tecture (the TAP controller is the state machine that controls
the TAPs operation) and can be expected to function in a
manner that does not conflict with the operation of devices with
IEEE Standard 1149.1-compliant TAPs. The TAP operates
using LVTTL/LVCMOS logic level signaling.
Disabling the JTAG Feature
It is possible to use this device without using the JTAG feature.
To disable the TAP controller without interfering with normal
operation of the device, TCK should be tied LOW (VSS) to
prevent clocking the device. TDI and TMS are internally pulled
up and may be unconnected. They may alternately be pulled
up to VCC through a resistor. TDO should be left unconnected.
Upon power-up the device will come up in a reset state which
will not interfere with the operation of the device.
Test Access Port (TAP)
TCK –Test Clock (INPUT)
Clocks all TAP events. All inputs are captured on the rising
edge of TCK and all outputs propagate from the falling edge
of TCK.
TMS – Test Mode Select (INPUT)
The TMS input is sampled on the rising edge of TCK. This is
the command input for the TAP controller state machine. It is
allowable to leave this pin unconnected if the TAP is not used.
The pin is pulled up internally, resulting in a logic HIGH level.
TDI –Test Data In (INPUT)
The TDI input is sampled on the rising edge of TCK. This is the
input side of the serial registers placed between TDI and TDO.
The register placed between TDI and TDO is determined by
the state of the TAP controller state machine and the
instruction that is currently loaded in the TAP instruction
register (refer to Figure 1). It is allowable to leave this pin
unconnected if it is not used in an application. The pin is pulled
up internally, resulting in a logic HIGH level. TDI is connected
to the most significant bit (MSB) of any register (see Figure 2).
TDO – Test Data Out (OUTPUT)
The TDO output pin is used to serially clock data-out from the
registers. The output that is active depending on the state of
the TAP state machine (refer to Figure 1). Output changes in
response to the falling edge of TCK. This is the output side of
the serial registers placed between TDI and TDO. TDO is
connected to the least significant bit (LSB) of any register (see
Figure 2).
Performing a TAP Reset
The TAP circuitry does not have a reset pin (TRST, which is
optional in the IEEE 1149.1 specification). A RESET can be
performed for the TAP controller by forcing TMS HIGH (VCC)
for five rising edges of TCK and pre-loads the instruction
register with the IDCODE command. This type of reset does
not affect the operation of the system logic. The reset affects
test logic only.
At power-up, the TAP is reset internally to ensure that TDO is
in a High-Z state.
Test Access Port (TAP) Registers
Overview
The various TAP registers are selected (one at a time) via the
sequences of ones and zeros input to the TMS pin as the TCK
is strobed. Each of the TAPs registers are serial shift registers
that capture serial input data on the rising edge of TCK and
push serial data out on subsequent falling edge of TCK. When
a register is selected, it is connected between the TDI and
TDO pins.
Read Cycle, Suspend Burst
Current
H
X
H
L
L-H
Q
Read Cycle, Suspend Burst
Current
H
X
H
L-H
High-Z
Write Cycle, Suspend Burst
Current
X
H
L
X
L-H
D
Write Cycle, Suspend Burst
Current
H
X
H
L
X
L-H
D
Truth Table (continued)[2, 3, 4, 5, 6, 7]
Operation
Address
Used
CE CE2 CE2 ADSP
ADSC
ADV
Write
OE
CLK
DQ
Partial Truth Table for Read/Write
FUNCTION
GW
BWE
BWa
BWb
BWc
BWd
Read
H
X
Read
H
L
H
Write one byte
H
L
H
Write all bytes
H
L
Write all bytes
L
X
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